EVP Strategic Partnerships, CEA-Leti
Sustainability In Semiconductor
Eco-Innovation Program Manager, CEA-Leti
Léa Di Cioccio is Director of Research at CEA-Leti. She is currently in charge of the CEA-Leti-Eco innovation program.
Since 1990, when she joined the organization, she has conducted research activities in materials, epitaxy, direct bonding, etc. in the fields of 3D integration and power components in the frame of collaborations with STmicrolectronics, SOITEC and in lots European projects. She is the author of more than 200 publications, 5 book chapters and 40 patents. Concerned by the socio-ecological transitions underway, she is working to introduce these new paradigms into the organization's research methodologies and strategy.
Business Director of the Silicon Technologies Division, CEA-Leti
Laurent Pain is graduated from the Ecole Nationale Supérieure de Physique de Grenoble in 1992. He received his Ph D after his work on DUV resists study. He joined CEA-LETI in 1996 to work on infra-red technology, and then came back to STmicroelectronics in 1999 working on 193nm and e-beam lithography technologies.
From 2008 to 2014, Laurent Pain leaded the lithography laboratory of the silicon technology division of CEA-LETI. He was also managing in parallel the industrial consortium IMAGINE dedicated to the development of multibeam lithography with MAPPER lithography BV.
Since July 2014, within the LETI Silicon Technology Division, he is now in charge of the business and the partnerships developments of the Silicon Technologies Platform Division.
Tech For Health
3d-ic Advanced Architecture
Hmi : Sense & Act
Tech For Embedded Ai
Head of Memory & Computing Laboratory, CEA-Leti
Dr. François Andrieu is CEA fellow and the head of Laboratory “Nano-devices for Memory and Computing” at CEA-Leti, Grenoble, France.
He has been strongly involved in the development of the Fully-Depleted-Silicon-On-Insulator (FDSOI) CMOS technology at Leti and with STMicroelectronics, where he was assigned between 2012-2015 in the process-integration and technology-to-design groups. His fields of interest are: NVM Resistive-RAM, In-Memory-Computing, advanced CMOS transistors, 3D-sequential integration.
He is the author or co-author of more than 34 patents, 240 conference abstracts or refereed journal articles, 11 invited papers and 3 book chapters. He received the IEEE senior grade in 2018, the European ERC consolidator grant in 2019 and the IEEE/SEE Brillouin award in 2018.
Telecom Line Director, CEA-Leti
Eric Mercier is currently in charge of supervising and coordinating TELECOM activities at CEA-Leti. He is graduated from the ENSEEIH of Toulouse, France, in 1991, focused on microwaves and antenna design (internship done at Alcatel Space / TAS, Toulouse, France).
After having held positions in the optical test equipment with Schlumberger, for physical fiber optical link tests, as analog and signal processing engineer, he has pursued his work in semiconductor companies like ST and Atmel as R&D Application & Characterization engineer, as well as Marketing engineer. His main field of interest has been low power RF dedicated to Wireless Sensor Network. With CEA-Leti, France, since 2006, he has led projects in the scope of ULP RF, with a specific focus on low-power RF transceiver design & implementation as well as on embedded resources dedicated to low-power WSN solutions.
After having been the Head Manager of the Laboratory for Architectures & Integrated RF design (LAIR), in charge of designing RF solutions for ULP, UWB, LPWA, mmW, high-data rate, RFID, PA, and FEM, with a common target of addressing the lowest possible power consumption and make use of the most advanced CMOS technologies, he is now Deputy Head of the Telecom & Wireless Unit at CEA-Leti in addition to the Telecom line positionhis. He has co-authored some conference papers, participated to a book chapter on the topic of WSN, and disseminated CEA-Leti Telecom activities in many various workshop, congresses and conferences