Speakers
Michael Tchagaspanian
EVP Strategic Partnership, CEA-Leti
Michael Tchagaspanian
EVP Strategic Partnership, CEA-Leti
Babak Sabi
Technical Advisor, Sabi Tech Advisory LLC
Babak Sabi
Technical Advisor, Sabi Tech Advisory LLC
Bio:
Dr. Babak Sabi Founder & Principal, Sabi Tech Advisory LLC
Dr. Babak Sabi is a veteran of the semiconductor industry with a career spanning more than four decades of technical and executive leadership. As the Founder of Sabi Tech Advisory LLC, he provides strategic counsel to global technology firms at the intersection of silicon manufacturing, advanced packaging, and cloud-scale AI infrastructure. Dr. Sabi’s career is defined by his long-standing tenure at Intel Corporation, where he served in several of the company’s most critical technical and operational roles. As Senior Vice President and General Manager of Assembly Test Technology Development (ATTD), he led the industrialization of the industry’s first 2.5D and 3D heterogeneous integration technologies. Crucially, Dr. Sabi also held a primary leadership role within Intel’s Corporate Quality Network (CQN). In this capacity, he was responsible for the rigorous quality and reliability standards required for high-volume manufacturing across multiple process nodes. Following his 40-year career at Intel, Dr. Sabi most recently served as Vice President of Technology at AWS (Annapurna Labs), where he oversaw the hardware engineering requirements for the world’s largest cloud infrastructure.
Abstract:
Hyperscalers are changing the landscape for chip development with specialized custom chips. They are becoming more vertically integrated. Additionally future challenges of Advanced Packaging are discussed.
Takaki Murata
Senior Vice President & Executive Board Member, Murata
Takaki Murata
Senior Vice President & Executive Board Member, Murata
Bio:
Takaki Murata has been involved in technology development, accounting, planning, and business management at the Company and its group companies for many years and corporate management as a chief officer at business companies in the United States, accumulating a wealth of experience and a solid record of achievement. He has been elected as a Member of the Board of Directors because the Company expects that he will continue to strengthen the decision-making and supervisory functions of the Board of Directors.
Abstract:
The rapid scaling of AI and high‑performance computing workloads is driving a fundamental transformation of data center power architectures, from on‑package integrated voltage regulators to high‑voltage power supply units. In this context, passive components are no longer commodities but critical system enablers.
This presentation introduces Murata’s silicon capacitor technologies and roadmaps, highlighting how continuous innovations in three‑dimensional charge density, voltage capability, and reliability unlock new design spaces for advanced power delivery. Leveraging deep‑trench and nanoporous architectures, Murata silicon capacitors combine ultra‑low ESL/ESR, exceptional thermal and frequency stability, predictable aging, and high customization flexibility.
We will illustrate how these characteristics enable thin, high‑frequency integrated voltage regulator modules close to processors, as well as high‑voltage silicon capacitors for next‑generation data center power supplies operating up to 800V nominal.
Tim Breen
Chief Executive Officer, GF
Tim Breen
Chief Executive Officer, GF
Bio:
Tim Breen is Chief Executive Officer (CEO) of GF, a position he was appointed to in 2025, having joined the company in 2018.
Prior to becoming CEO, Mr. Breen served as GF’s Chief Operating Officer (COO), overseeing the company’s global operations, including the manufacturing, quality, supply chain and digital transformation teams. Earlier in his tenure at GF he held various executive roles including leading strategy, business transformation and finance. Prior to joining GF, Mr. Breen served as a member of the senior leadership team of GF’s founding shareholder, Mubadala Investment Company (Mubadala). Earlier in his career, he was a partner with McKinsey & Company in Abu Dhabi.
Mr. Breen holds a Master of Business Administration degree from London Business School and is based in New York.
Hajime Shoji
Executive Officer, General Manager of Transmission Devices Laboratory, Sumitomo Electric Industries
Hajime Shoji
Executive Officer, General Manager of Transmission Devices Laboratory, Sumitomo Electric Industries
Bio:
Hajime Shoji received the Ph.D. degree in electronic engineering from the University of Tokyo, and joined Fujitsu Laboratories in 1990. He moved to Eudyna Devices, a joint venture of Fujitsu and Sumitomo Electric in 2004, then after the change in organization, moved to Sumitomo Electric Industries, LTD. in 2009. He has been consistently leading the development of compound semiconductor materials and devices for optical and microwave communications. Currently, he is serving as a general manager of the Transmission Devices Laboratories, and also as an executive officer of Sumitomo Electric.
Abstract:
Optical device technologies play a fundamental role in combination with electronics toward photonics-electronics convergence. In the presentation, our development activities focusing on heterogeneous integration of III-V compound semiconductor and silicon and its application to advanced optical devices will be described. Photonics-electronics integration platform technologies will be also presented together with topics on some related devices.
Audrey Charles
Senior Vice President of Corporate Strategy & Advanced Packaging; President of Lam Capital
Audrey Charles
Senior Vice President of Corporate Strategy & Advanced Packaging; President of Lam Capital
Bio:
Audrey Charles is senior vice president of corporate strategy and advanced packaging, and president of Lam Capital at Lam Research. In this position, she is responsible for leading the executive management team in the development of strategic priorities and key initiatives that support the company’s long-term profitable growth. She is also responsible for accelerating the company’s market-leading position in advanced packaging to deliver differentiated technology and support to customers.
Additionally, Audrey oversees Lam’s Corporate Development team and investment arm, Lam Capital, which invests in disruptive companies that advance the semiconductor ecosystem through next generation industrial automation, technology and product innovation, and new market opportunities. She brings a broad base of experience to her role, including engineering, customer technology management and investor relations. Since joining Lam in 1995, she has served in a range of leadership positions including senior vice president of Global Human Resources and vice president of corporate initiatives.
Audrey earned an M.B.A. from the MIT Sloan School of Management and a B.S. in applied physics from Dublin City University.
Thomas Rueckes
Chief Executive Officer, FMC
Thomas Rueckes
Chief Executive Officer, FMC
Bio:
Thomas Rueckes is a senior semiconductor executive and inventor with deep expertise in advanced memory technologies, company building, and industrial-scale execution. He is currently CEO of Ferroelectric Memory Company (FMC), where he leads the development and commercialization of high-performance non-volatile memory products spanning NV-DRAM+ in Memory Fabs and high density Near Compute Memory, 3D-CACHE+ in advanced logic foundries. His work bridges materials, devices, integration, packaging, and system-level deployment, with active engagement across tier-1 memory IDMs, hyperscalers, OEMs, and leading equipment and materials suppliers.
Previously, Dr. Rueckes was Co-Founder, CTO, and COO of Nantero, where he spent more than two decades building one of the industry’s most advanced emerging memory platforms, overseeing R&D, operations, manufacturing scale-up, IP strategy, fundraising, government programs, and strategic partnerships. He holds more than 200 granted patents and has published extensively in leading scientific journals. Dr. Rueckes earned his Ph.D. in Nanotechnology from Harvard University, with earlier training in surface science at Imperial College London UK as well as chemistry and physics at Philipps University of Marburg, Germany. He is bilingual in English and German and brings extensive experience translating deep science into globally competitive semiconductor products and companies.
Bill Chang
Co-founder, President & CTO, Density AI
Bill Chang
Co-founder, President & CTO, Density AI
Bio:
Bill Chang is the Co-founder, President, and Chief Technology Officer of DensityAI, a company focused on making AI infrastructure radically more efficient and sustainably scalable, by building the world's densest AI compute platform, integrating innovations across technology, chip and system architecture, software, and datacenter infrastructure.
Prior to founding DensityAI, Chang served as Chief System Architect at Tesla, where he was responsible for the design and architecture of the Dojo supercomputer, a vertically integrated high-performance AI training system. He led the development of the first production wafer-scale package technology, enabling machine learning training to scale to exaFLOP levels.
Before Tesla, Chang was at Apple, where he managed the transition of the Mac platform to Apple Silicon. Earlier in his career, he held various technical leadership roles at IBM Microelectronics spanning DRAM, CMOS technology development, and manufacturing, building deep expertise in silicon design and semiconductor process engineering.
Len Koh
Senior Director, Powerchip Semiconductor Manufacturing Corp.
Len Koh
Senior Director, Powerchip Semiconductor Manufacturing Corp.
Bio:
Len Koh is Senior Director of Project Management at Powerchip Semiconductor Manufacturing Corp. (PSMC), driving innovation at the intersection of AI computing architecture and advanced memory technologies. With over two decades in the semiconductor industry, he has led initiatives in Processing-in-Memory (PIM) and 3D DRAM stacking to overcome data movement bottlenecks in next-generation systems. Holding multiple international patents, Len focuses on redefining the convergence of memory and compute to power the future of intelligent computing. He earned his Master’s degree in Computer Science from National Tsing Hua University
Abstract:
The surging AI workloads demand a memory fabric that delivers massive bandwidth, ultra-low power, and truly effective performance. Emerging bandwidth-centric solutions — wide-bandwidth memory, near-memory computing, and in-memory computing — aim to meet these challenges. Effective AI systems require co-designing memory and compute architectures to suit specific workloads. This lecture will explore the trends, compare the solutions, and underscore the need for tailored memory approaches.
Chih-I Wu
Vice President & Senior Expert, ITRI
Chih-I Wu
Vice President & Senior Expert, ITRI
Bio:
Dr. Chih-I Wu is the VP and Senior Expert at Industrial Technology Research Institute (ITRI), as well as a professor in Graduate Institute of Photonics and Optoelectronics and Department of Electrical Engineering of National Taiwan University. He was the General Director of Electronic and Optoelectronic System Research Laboratories, ITRI, from 2015 to 2022. His research is mainly on 2D material and devices, organic optoelectronics, metal-semiconductor interfaces, and heterojunctions. Prior to joining NTU, he worked at Component Research Lab of Intel in the US from 2000 to 2004. His work at Intel was mainly on developing the advanced VLSI process technology, such as Cu and low k interconnects, metal gate materials, and atomic layer deposition process. Dr. Wu got his B.S. degree from National Taiwan University and M.S. degree from Northwestern University, both in Physics. He received his Ph.D. from Princeton University in Electrical Engineering.
Abstract:
In the talk, I will share with you ITRI’s strategy on internation collaboration. I will start from the evolution of Taiwan’s semiconductor ecosystem, from 1970’s till now. The current status and the future of both Taiwan and global semiconductor industry will also be presented from our perspective. Based on the evolution and future prediction of semiconductor ecosystem, ITRI’s strategy on international collaboration will be discussed in this presentation.
Elliott Mc Namara
SVP & Head of the 3D DUV, ASML
Stuart Knight
President, HORIBA Group Corporate Officer
Stuart Knight
President, HORIBA Group Corporate Officer
Bio:
Stuart Knight is Materials and Semiconductor Strategy Director and HORIBA Group Corporate Officer, with more than three decades of experience in the global semiconductor industry. He began his career in 1992 in Hong Kong, working for a back‑end semiconductor equipment manufacturer, gaining first‑hand experience of high‑volume manufacturing environments in South East Asia.After returning to Europe in 1998, Stuart joined HORIBA, where he helped establish and grow the company’s semiconductor portfolio, delivering process monitoring and control solutions for semiconductor process optimisation to customers across Europe and globally. He spent many years building HORIBA’s presence in the semiconductor segment before moving into senior executive leadership.
Today, Stuart contributes actively to European and global semiconductor strategy for the HORIBA Group, bringing a practical, manufacturing‑led perspective to industry discussions
Abstract:
The semiconductor industry is increasingly defined by system level complexity, where performance, yield, and sustainability depend on the ability to sense, measure, and control interactions across the entire value chain.
HORIBA addresses this challenge through a woven value chain of sensing and metrology solutions, connecting materials characterization, process monitoring, device performance, and fab and sub fab environments. Built on decades of expertise in analytical instrumentation and supported by a strong global footprint, this integrated approach enables continuous insight from upstream R&D to high volume manufacturing.
By connecting core technologies, product organizations, and global operations, sensing and metrology emerge as a strategic enabler for innovation, yield, and industrial resilience. This integrated approach illustrates how semiconductor leaders can shape scalable growth, accelerate technology adoption, and support a more sustainable semiconductor ecosystem.
John Neuffer
President & Chief Executive Officer, SIA
John Neuffer
President & Chief Executive Officer, SIA
Bio:
John Neuffer is President and CEO and ex officio board member of the Semiconductor Industry Association (SIA), which has been the voice of the chip industry for nearly five decades. He has been at the nexus of technology, public policy, and trade for most of his career. Since joining SIA in 2015, John has led the association’s policy advocacy in Washington and capitals around the world to foster growth and innovation in semiconductor design, manufacturing, and research.
John also serves as a member of the Board of Directors of the Semiconductor Research Corporation, the world’s leading non-profit industry-government-academia microelectronics research consortium. Additionally, he is a member of the Science & Technology Action Committee and the Council on Foreign Relations.
Prior to joining SIA, John served as Senior Vice President for Global Policy at the Information Technology Industry Council, where he led a global team to expand market access opportunities for member companies around the world. He directed all global government relations in trade, cybersecurity, standards, regulatory, Internet governance, and privacy.
Previously, John served for over seven years at the Office of United States Trade Representative (USTR) in Washington, DC: two years as Deputy Assistant U.S. Trade Representative for Asia-Pacific Economic Cooperation (APEC) Affairs, preceded by over five years as Deputy Assistant U.S. Trade Representative for Japan.
Prior to his tenure with USTR, John was a Senior Research Fellow and Political Analyst with the Mitsui Kaijyo Research Institute in Tokyo for nine years. As a leading commentator on Japanese politics and policy at the institute, he published a widely read newsletter and wrote regular commentary for the Asian Wall Street Journal, TheStreet.com and Newsweek Japan. All told, John lived in Japan 11 years. He is a native of Montana and Washington State.
Dr. Atsuyoshi Koike
Chief Executive Officer, Rapidus corporation
Dr. Atsuyoshi Koike
Chief Executive Officer, Rapidus corporation
Bio:
ATSUYOSHI KOIKE established Rapidus Corporation, a Japanese advanced logic semiconductor company in August 2022. Prior to this role, Koike had served as President of Western Digital Japan since April 2018. Prior to joining Western Digital, he held the position of president and chief executive officer at Trecenti Technologies, Inc., as well as served as corporate chief engineer for Renesas Technology Corporation. Prior to that, he held senior manufacturing management and executive leadership positions at Hitachi, Ltd. Koike received the B.S. and M.S. in Materials Science and Engineering from Waseda University and Ph.D. in Electronic Engineering from Tohoku University.
Alexandre Shirakawa
VP of Engineering, SKYWORKS
Sébastien Dauvé
Chief Executive Officer, CEA-Leti
Sébastien Dauvé
Chief Executive Officer, CEA-Leti
Bio:
Sébastien Dauvé was named CEO of CEA-Leti effective on July 1, 2021, after more than twenty years of experience in microelectronics technologies and their applications, including clean mobility, medicine of the future, cybersecurity, and power electronics.
Sébastien Dauvé started his career at the French Armament Electronics Center, where he worked on developing synthetic-aperture radar. In 2003, he joined CEA-Leti as an industrial transfer manager and supervised several joint research laboratories, in particular with the multinational Michelin.
In 2007, Sébastien Dauvé became a laboratory manager, then head of an R&D department in the area of sensors applied to the Internet of things and electric mobility. During this time, he supported the dissemination of new technologies in industry, including the automotive industry (Renault), aeronautics, national defense (SAFRAN), and microchips with the industry leader Intel. He played an active role in the creation of start-ups in application fields ranging from health to infrastructure security, leading to dozens of new jobs. In 2016, he became Director of the CEA-Leti Systems Division.
From sensors to wireless communication, Sébastien Dauvé has played an active role in the digital transformation, focused on coupling energy frugality and performance. He has made cross-disciplinary approaches central to innovation by harnessing the expertise of talented teams with diverse backgrounds. Their goal is to provide technological tools for meeting the major societal challenges of the future.
Sébastien Dauvé is a graduate of the French Ecole Polytechnique and the National Higher French Institute of Aeronautics and Space (ISAE-SUPAERO).
Jean-René Lèquepeys
Deputy Director and Chief Technology Officer, CEA-Leti
Jean-René Lèquepeys
Deputy Director and Chief Technology Officer, CEA-Leti
Bio:
Jean-René Lèquepeys received an engineering degree in 1983 from CentraleSupélec, a top French graduate engineering school at Paris-Saclay University, France. He taught physics during 2 years in Ouarzazate, Morocco.
He joined CEA, a French Research and Technology Office focusing on applied research, in Paris Saclay in 1985. He first worked at the laboratory of the Central Security Office, on the evaluation of means of detection and intrusion. Two years later, he was promoted head of this laboratory.
In 1993, he moved to Grenoble, France, and joined the System Division of CEA-Leti. He worked on different projects in the field of image processing and telecommunication technologies. In particular, he was responsible for the "Telecom, Communicating Objects and Smart Card" programs from 1999 to 2004.
In 2005, he took the responsibility of the Circuits Design Division at CEA-Leti (200 people). He launched new research activities at CEA such as a new laboratory in Aix-en-Provence, France, on the development of secured chips. In 2000, Jean-René Lèquepeys received the prestigious award from the french Société de l'Electricité, de l'Electronique et des technologies de l'information et de la communication (SEE) "Grand Prix de l'électronique Général Ferrié" for his work in the telecommunications field (he holds 15 patents).
In 2010, he launched a new division at CEA focusing on Electronic Architectures, Integrated Circuit Design and Embedded Software. He established the structure on two sites (Paris and Grenoble) and led the division twice in his career.
He rapidly got involved in the creation of the Silicon Components Division at CEA-Leti, and took the lead of it in 2011 managing 350 people. Division encompasses micro and nanoelectronics (SOI, nanodots, quantum, memories, 3D technologies, substrates), Micro Systems (sensor, actuator, radiofrequency components) and Power Components. He established the French Nano2022 Program for research funding in microelectronics.
In 2019, he was appointed Chief Technology Officer of CEA-Leti, overseeing Science, relations with the European Commission, Industrial Partnership and Strategic Program Management in the scope of the institute (2,000 people, ~€350m budget). He took the responsibility of the Microelectronic Program at CEA level, spearheading technological and upstream research in the field of semiconductor technologies. For the past 2 years, he has been strongly involved in the CEA-Leti Next Gen FD-SOI project in the frame of France2030 and has played a key role in European chips Act pilot line promoting FD-SOI and Gate All Around technologies.
Having dedicated his career to applied research, he is regularly invited as a keynote speaker in international semiconductor conferences.
Jean-René is also Vice President of ACSIEL, a professional trade union gathering industrial companies in the French electronic value chain, member of the Board of EPOSS, the European Technology Platform on Smart Systems Integration, a member of the Board of AENEAS, the Association for Europoean NanoElectronics Activities, and an expert consultant for the European Commission and French Research Agency
Data & Network/Cloud Convergence
Hakima Chaouchi
Full Professor, Telecom SudParis – Institut Polytechnique de Paris
Hakima Chaouchi
Full Professor, Telecom SudParis – Institut Polytechnique de Paris
Bio:
Hakima Chaouchi is a Full Professor at Telecom SudParis – Institut Polytechnique de Paris. Following her PhD from Sorbonne University and King’s College London, she has dedicated 25 years of research to the optimization of wireless and mobile networks, the Internet of Things (IoT), cybersecurity, 5G/6G networks, and emerging concepts such as N3C and the digital continuum. For the past two years, she has served as the Head of Strategy for Digital Sovereignty and Sobriety at Institut Mines-Télécom, she is a member of the ASIC national research program agency of the high minitry of research and education and space (MESRE), specifically for the networks and digital continuum axis. As a former Scientific Advisor to the French Ministry of Higher Education and Research (MESRE), where she played a key role contributing to the structuring of the French academic research under the France 2030 initiative (specifically the Cyber, Cloud, and Telecom research, innovation and competences programs). She also contributed to both the national and European (ESFRI) roadmaps for digital research infrastructures. An expert in European networking and telecom working groups, she is the Vice-Chair of the States Representatives Group for the European JU SNS (Smart Networks and Services) and Chairs the Intermediary Supervisory Board of the ESFRI SLICES research infrastructure. Highly active in global standardization, she has chaired several ITU-T focus groups on data management and eco-responsible AI, while contributing to IETF and ETSI working groups. She currently leads the France 6G national mission, focusing on the 6G R&D ecosystem and the standardization engagement within the French national strategy for the 5G and Future Networks acceleration coordinated by the general directorate of entreprises (DGE).
Hughes Metras
Director of ASIC, Component and Digital Infrastructure French Program Agency
Hughes Metras
Director of ASIC, Component and Digital Infrastructure French Program Agency
Bio:
Hughes Metras has been appointed director of the National Program Agency for Components, Systems and Digital Infrastructures (ASIC) on September 15th, 2025. Previously, he led the IRT Nanoelec, a consortium of industrial and academic members, conducting research in the field of 3D stacking technologies, silicon photonics and embedded components. He also spent 6 years in California, as VP of strategic partnerships for the US region where he established Cea Leti’s commercial office in 2011. He benefits from a technical background in Physics engineering (Ecole Centrale de Marseille) and holds an MBA from the University of Miami (Florida).
The program Agency ASIC has been created 2 years ago to build a strategic vision for the french research ecosystem in the field of HW technologies from material science and engineering to components, systems and network + compute infrastructures. The agency is launching three programs adressing challenges in the fields of (i) AI Accelerators, (ii) IC design methodologies and (iii) Packaging through the engagement of academic and technology research communities.
Edgar Auslander
Senior Director, Strategic Partnerships, Wearables, AR, AI, Meta
Edgar Auslander
Senior Director, Strategic Partnerships, Wearables, AR, AI, Meta
Bio:
Edgar Auslander has more 35 years of experience serving at company Boards, startups, a VC, and Fortune 100 companies. As Senior Director of Strategic Partnerships at Meta, he initiated and drove the partnership with EssilorLuxottica resulting in Ray-Ban Meta smart glasses. He is the Founding Managing Partner at Menlo Business Partners and was one of the founders of Texas Instruments' Wireless Business, bringing it from scratch to $5B/year. A former Faculty Member at Stanford University and the EDHEC Business School, he teaches Management of Change and Business Negotiation classes at UC Berkeley Extension. A Senior Member of IEEE, he is a Kauffman Fellow and holds an MBA from Columbia University, and an MEEng. from Cornell University.
Cristell Maneux
Professor, University of Bordeaux
Cristell Maneux
Professor, University of Bordeaux
Bio:
Cristell MANEUX received the M.Sc. degree in electronics engineering and the Ph.D. degree in electronics from the University of Bordeaux, Bordeaux, France, in 1994 and 1998, respectively. From 1998 to 2012, she has been Associate Professor in IMS Laboratory, Department of Sciences and Engineering, University of Bordeaux, France. Since 2012, she is Professor in the same laboratory, for which she has been the director since January 2022. Her research interests focus on Compact modelling of advanced and emerging devices: InP HBT, SiGe HBT, Carbon NanoTube Transistors, Nanowire Transistors; Device electrical characterization: DC, RF, pulsed, Low Frequency noise, RTS Noise; Device failure mechanisms and integrated circuit reliability; THz integrated devices for Beyond 5G communications; Unconventional nanoelectronics.
She has co-authored more than 200 publications on high-impact journals and conferences. She serves as Technical Program Committee member and/or reviewer for DATE, EuMW, Euro-SOI, ISCAS, NEWCAS, and ESSDERC. Since 2022, Prof. Maneux is member of the Editorial Board of IEEE Transaction of Computer Aided Design and since 2020 she is member of the Editorial Advisory Board of Solid State Electronics.
Abstract:
The upcoming explosion of AI and HPC workloads, the rising demand for data centers and cloud storage, and the expansion of IoT and edge computing are driving the need for next-generation memory and storage solutions, as well as the adoption of emerging technologies for connectivity .
This presentation features some technologies and techniques for achieving emerging hardware in the fields of Storage and Connectivity.
Takahiro Ogura
President of AI Computing Division, Preferred Networks
Takahiro Ogura
President of AI Computing Division, Preferred Networks
Bio:
Takahiro Ogura is a seasoned leader in high-performance computing with over 20 years of experience. He currently heads the AI Computing Division at PFN, overseeing the company's critical computing infrastructure technologies including the MN-Core™ series of AI semiconductors and in-house supercomputers. Prior to joining PFN, he served as the after-sales service manager for domestic high-performance computing clients at Fujitsu, where he began his career as a systems engineer working on supercomputer systems projects. A notable career highlight was his instrumental role in the design and development of the Fugaku (Post-K) supercomputer at Japan's national research and development agency RIKEN. Ogura received a Master's degree from Tsukuba University's Systems and Engineering program in 2005.
Abstract:
As generative AI continues to evolve, the importance of inference computing is poised to grow steadily. In this session, the speaker Takahiro Ogura will introduce the 3D-stacked memory structure, a technological breakthrough for AI inference chips, and demonstrate its potential for social transformation through AI agents and edge AI. Ogura will also share his company Preferred Networks’s vision for democratization of AI and creation of new paradigms through their proprietary chip design, ecosystem development and industry collaborations.
Semiconductors for Computing
François Andrieu
Head of Memory & Computing Laboratory, CEA-Leti
François Andrieu
Head of Memory & Computing Laboratory, CEA-Leti
Dr. François Andrieu is CEA fellow and the head of Laboratory “Nano-devices for Memory and Computing” at CEA-Leti, Grenoble, France.
He has been strongly involved in the development of the Fully-Depleted-Silicon-On-Insulator (FD-SOI) CMOS technology at Leti and with STMicroelectronics, where he was assigned between 2012-2015 in the process-integration and technology-to-design groups. His fields of interest are: NVM Resistive-RAM, In-Memory-Computing, advanced CMOS transistors, 3D-sequential integration.
He is the author or co-author of more than 34 patents, 240 conference abstracts or refereed journal articles, 11 invited papers and 3 book chapters. He received the IEEE senior grade in 2018, the European ERC consolidator grant in 2019 and the IEEE/SEE Brillouin award in 2018.
Olivier Thomas
Deputy Head of the Digital IC Division, CEA-List
Olivier Thomas
Deputy Head of the Digital IC Division, CEA-List
Bio:
Olivier THOMAS is the deputy head of the Digital IC & System Design Division at CEA-List. He is in charge of partnership strategies and ecosystem growth, leveraging his background in system/design-to-technology co-optimization and product engineering within the field of embedded systems innovation. He is author and co-author of 25 patents and 77 publications. He was a pioneer and co-inventor of multi-VT technology utilizing back biasing for FD-SOI, as well as single p-well SRAM. He got is PhD in 2004 from the doctoral school of Computer Science, Telecommunications, and Electronics of Paris.
Shigeru Kawanaka
Director, Corporate R&D Institute, KIOXIA
Shigeru Kawanaka
Director, Corporate R&D Institute, KIOXIA
Bio:
Shigeru Kawanaka joined Toshiba ULSI research laboratory in 1991.
Here, his research interest was high speed Logic device mainly SOI CMOS.
From 2002 to 2005, he worked on the joint development project of high-end microprocessor between Toshiba, Sony, IBM and AMD for the target of super computer, game and consumer products.
From 2006 to 2016, he engaged advanced device research activity with low power CMOS, high-density memory, power IC and image sensor.
In 2016, he served senior manager of advanced memory technology department. At this time, he started his research management carrier focusing on high speed memory device.
From 2023, he served director position of corporate Frontier R&D institute of KIOXIA corporation.
Abstract:
Recent computing system reforms have gone beyond the conventional scaling guidance principles and accelerated evolution based on the emergence of new algorithms and market requirements. This presentation introduces the evolution of the AI world and the new technological transformation based on the interlocking of memory devices from the system level that supports this evolution, especially the evolution of technologies that respond to the accelerating increase in data transactions.
Juan Rey
CTO, Siemens EDA
Juan Rey
CTO, Siemens EDA
Bio:
Juan C. Rey returned to the Calibre Segment and was appointed as Sr. Vice President, Segment Leader/General Manager for Siemens EDA in April of 2025. Prior to his appointment as GM, Juan led the Central Engineering Solutions Team as part of a government program focused on 3D flows. He Transitioned to Central Engineering Solutions Team after serving as Vice President of Government Programs for Siemens EDA where he was responsible for defining technical programs to support government initiatives since 2023. Prior to his work with Government Programs, Juan held the roll of Vice President of Calibre Engineering. He joined Mentor Graphics in 2001 as Senior Engineering Director for Mentor?s industry-leading Calibre product line, directing all development activities for Calibre products, a role he performed until December 2021. Prior to his time at Mentor Graphics, Juan was Vice President of Engineering at Exend Corporation, managing all software development and quality activities. He joined Extend after serving as Engineering Director of Physical Verification at Cadence Design Systems. Earlier positions include Manager/Developer for Process Modeling and Parasitic Extraction at Technology Modeling Associates, Visiting Scholar/Science and Engineering Associate at Stanford University, Senior Research Engineer at INVAP, Argentina, and Associate Professor at Universidad Nacional del Comahue, Argentina. Juan holds a degree in Nuclear Engineering from Universidad Nacional de Cuyo, Argentina. The author or co-author of numerous papers and conference presentations, he serves on the Executive Technology Advisory Board of Semiconductor Research Corporation (SRC) and the UCLA Center for Domain-Specific Computing.
Sven Beyer
Technology Architect, Global Foundries
Sven Beyer
Technology Architect, Global Foundries
Bio:
Sven Beyer received his master’s and Ph.D. in Physics from the University of Hamburg, Germany. He started his career with Infineon as a manufacturing engineer in the etch department in 2003. Joining the integration department of AMD in 2005, he intermediately spent a year in the IBM ASTA alliance 2007 working on the 45nm node. Returning to Dresden, Sven has worked in many roles since then, ranging from integration technology-lead to customer engineering and lasting throughout the separation of GlobalFoundries and AMD. Today he serves as DMTS in GlobalFoundries FAB1 as technology architect (TA), overseeing mainly the eNVM & CMOS roadmap and development in Dresden.
Abstract:
Introducing the “AI stack” at the example of transformer-based AI and laying out current and potential future ownership of the elements of this stack, I will make the daring claim that “Attention ain’t everything”. Hence, pushing the digital brute force computing capability of leading-edge CMOS alone, by continuing to stumble along the path of Moore’s law, will likely never deliver true human like intelligence. Perusing this way, striving for true human like intelligence, power consumption will sky-rocket, eventually building an insurmountable barrier. It will need another paradigm shift, already foreseeable at the horizon, to lift AI capabilities on a manageable power budget, to the next level. Here the value-added solution (VAS) device offerings of mature CMOS nodes, like non-volatile memory cells, in combination with specialized low power CMOS platforms, might play a crucial role. In addition, financially affordable CMOS technologies bear the chance to bring this fascinating technology into the edge devices.
Shu-Jen Han
CTO, SEEQC
Shu-Jen Han
CTO, SEEQC
Bio:
Shu-Jen Han currently serves as a CTO of SEEQC, where he is leading global multi-disciplinary teams to develop chip-based quantum computing systems. He is responsible for company’s technology roadmaps, and the integration of SEEQC’s digital chip solution into clients’ quantum systems. Before SEEQC, Han was an associate VP of HFC Semiconductor Corp., where he drove two generations of MRAM technology development. Prior to HFC, he managed nanoelectronics group at IBM T. J. Watson Research Center. He obtained his Ph.D. degree from Stanford University. He has authored over 100 technical publications, including multiple publications in Science and Nature series, two book chapters, and over 200 issued US patents.
Abstract:
Current superconducting quantum computers rely on a brute-force scaling approach where quantum chips operating at the millikelvin stage inside dilution refrigerators are connected to room-temperature electronics via an ever-increasing number of signal wires. In order to drastically scale up such systems without facing refrigeration challenges, these quantum interface electronics need to be integrated at cryogenic temperatures, ideally at the same stage as qubits. Here, we show that, by employing energy-efficient digital superconducting microchips based on single flux quantum technology, all essential functions to operate a full stack quantum computer can be integrated at 10 mK.
Cécilia Dupré
Quantum Devices lab Manager, CEA-Leti
Eric Guthmuller
Research Engineer, CEA-List
Eric Guthmuller
Research Engineer, CEA-List
Bio:
Eric Guthmuller graduated from Ecole Polytechnique and received the M.S. degree from Telecom Paris, France in 2009. He received his Ph.D in computer science from the University Pierre & Marie Curie (UPMC, Paris, France) in 2013. He joined the CEA-Leti in Grenoble as a full-time researcher until 2019, then within CEA-List. His main research interests include processor architectures and their memory hierarchy, and quantum computer control architectures.
Michael Schaffert
SVP, Robert Bosch
Michael Schaffert
SVP, Robert Bosch
Bio:
Michael studied electrical engineering at the Technical University of Stuttgart.
In 1998, he joined Bosch in Stuttgart as hardware development engineer for Engine Control Units. 2001, he joined ETAS GmbH in Stuttgart as a Product Manager for Rapid Prototyping system. He left ETAS 2011, when he was Director for Product Management and Development and responsible for all ETAS HW. After ETAS Michael became Vice President at BOSCH and was the Head of Center of Competence for Vehicle Electrics and Electronics Architecture. In this role he was responsible for future E/E-Architecture’s development incl. responsibility for recognizing and assigning new technologies. In 2015 he moved to BOSCH Japan and was the Head of Customer Engineering responsible for Asian Pacific Engine Control Units & SW Service Business. In 2019 he came back to Germany and became Head of HW Development for Powertrain Control Systems BOSCH. In 2020 he was founding member of the new BOSCH Division XC (Cross-Domain Computing Solutions) and had the role as the head of Product Group responsible for Base-SW and Middleware incl. OS Product & Services. Since 07/2022 he joined BOSCH Tier2 as a SCP responsible for Chiplet.
Abstract:
The CHASSIS initiative marks a transformative step in automotive compute platform design for Software-Defined Vehicles (SDVs). By leveraging chiplet-based architectures, CHASSIS addresses the inherent limitations of traditional monolithic System-on-Chips (SoCs), introducing a modular and scalable approach to semiconductor design. This paradigm shift enables tailored, high-performance computing solutions that accelerate the transition to software-defined mobility and foster competitive innovation across the automotive industry.
Our vision extends beyond technical advancement: CHASSIS aims to restore European technological sovereignty in automotive semiconductor innovation through the creation of a multi-vendor chiplet ecosystem. This ecosystem ensures architectural flexibility, automotive-grade reliability, and freedom from proprietary constraints, paving the way for open, future-proof compute platforms.
By delivering scalable architectures that meet diverse performance requirements,
Semiconductors for Defense
Rachid Jaoui
Head of Innovation for Nanotechnologies, DGA/AID
Rachid Jaoui
Head of Innovation for Nanotechnologies, DGA/AID
Bio:
Head of innovation for nanaotechnologies at the French Defence Innovation Agency (AID); I work closely with industry, research institues, and start up to foster innovation and strengthen technological sovereignty.
Abstract:
Semiconductors are at the heart of modern defense systems and are essential to maintaining technological superiority. However, France and Europe remain highly dependent on non-European supply chains amid rising geopolitical tensions. This talk will highlight the vulnerabilities this creates and their operational implications. It will also outline the key levers to strengthen our technological autonomy. The overarching goal is to secure the long-term sovereignty and freedom of action of our armed forces
Ignacio Montiel Sanchez
Project Manager Defence Development Programme, European Commission - DG DEFIS
Ignacio Montiel Sanchez
Project Manager Defence Development Programme, European Commission - DG DEFIS
Bio:
Dr. Ignacio Montiel-Sánchez is a researcher and policy officer with extensive experience in defence technologies and a growing focus on the integration of artificial intelligence (AI) and semiconductor advancements into security and military applications. Currently employed at the European Commission's DG DEFIS, he supports the coordination of technical working groups with an emphasis on AI and semiconductors, contributing to the development of projects under the European Defence Fund (EDF). His research examines how AI and semiconductor technologies can enhance sensor capabilities, provide information superiority, improve operational efficiency, and tackle emerging challenges in modern defence systems. His work underscores the importance of collaboration across European institutions and industry to foster innovation and resilience in semiconductor and AI integration for defence purposes.
Abstract:
During this exciting period of advanements in semiconductor technology, the European Union is leading efforts to develop semiconductor technologies that are crucial for defence purposes.This presentation will highlight collaborative efforts between EU member states, industry leaders, and research institutions to drive technological progress. Key discussions will centre on policy frameworks, funding avenues, cross-border collaborations, and the integration of sustainable practices in semiconductor development. The presentation will address challenges such as supply chain security and technological independence, offering strategic pathways to ensure resilience and sustain innovation.
Cyrille Le Royer
Semiconductor Device Researcher, CEA-Leti
Cyrille Le Royer
Semiconductor Device Researcher, CEA-Leti
Bio:
Dr. Cyrille Le Royer is a Senior Expert at CEA-Leti, specialized in advanced semiconductor (Si, SiGe, Ge; GaN, SiC) devices.
With 20+ years of experience, he has driven advancements in 28, 14 and sub 12 nm Fully Depleted (FD-SOI) technologies (and other innovative transistors for CMOS ICs) collaborating with industry leaders like STMicroelectronics, IBM, Soitec and GlobalFoundries.
Since 2018 he is involved in the Power Device activity in CEA-Leti: from GaN based HEMTs to now high-efficiency SiC power devices, he bridges academia and industry to shape next-gen microelectronics.
Dr. Le Royer has supervised 10 PhD students, led several French (including ANR projects) and European R&D projects (on FDSOI and Power) and authored 180+ publications (h-index: 31) and 34 patents.
Abstract:
In a world where supply chain disruptions and geopolitical tensions threaten critical technologies, Europe must secure its own power electronics sovereignty. Through the CARTHAGE project, CEA-Leti is developing next-gen SiC thyristors for dual-use applications—from grid resilience to defense systems—while offering agile, sovereign manufacturing to meet urgent operational needs. This talk will explore how we’re bridging the gap between lab innovation and battlefield-ready components.
Alan Peyaud
Senior Research & Development Engineer, CEA-Leti
Mantas Sakalas
RF Group lead, Baltic Institute of Advanced technology
Mantas Sakalas
RF Group lead, Baltic Institute of Advanced technology
Bio:
Dr. Mantas Sakalas received a Master’s degree in electrical engineering from Berlin University of Technology in 2012. He continued his career in the industry working as an engineer in the field of microwave electronics components for radar applications. Since 2018 he is the leader the RF Group in Baltic Institute of Advanced Technologies (BPTI) in Vilnius, Lithuania. In 2024, parallel to his work as the RF group leader in BPTI, he acquired a PhD in Dresden University of Technology in the field of MIMO radars. The main focus of his research is development of MMIC components for radar and EW applications.
Abstract:
Establishing all European supply chain for RF components is one of the key goals in strengthening the European strategic autonomy. This is especially true for defense applications, where Europe is still falling behind and is strongly dependent on overseas supply.
However, there is a number of challenges that need to be overcome for Europe to create its own supply chain for defense systems. A lack, or even absence of commercial, open semiconductor foundries offering services for defense application development, limited technology offering, need for advanced packaging techniques. How can we tackle these challenges? Insights will be shared from European design house point of view.
Mathilde Cartier
IR Imaging Partnership Manager, CEA-Leti
Pierre-Damien Berger
MEMS Industrial Partnership Manager, CEA-Leti
Pierre-Damien Berger
MEMS Industrial Partnership Manager, CEA-Leti
Bio:
Pierre Damien Berger is MEMS Industrial Partnerships Manager at CEA LETI.
CEA LETI is a leading MEMS R&D lab working for industry, with more than 150 people working on these topics – world’s largest MEMS R&D institute.
Pierre-Damien was previously the MinaSmart (European Digital Innovation Hub) director at Minalogic. He worked before as CPS European projects manager, Head of Smart Devices Program, Industrial Partnership Manager and VP Business Development & Communication at CEA-Leti.
With more than 25 years of experience, 10 years in industry, 15 years in R&D serving industry, his experience has allowed him to master the right balance between business and innovation - Understand and listen to needs, identify and select innovative solutions, enhance the functions that meet expectations, communicate to radiate.
Philippe Robert
CEO, iNGage
Philippe Robert
CEO, iNGage
Bio :
Philippe Robert is CEO and co-founder of iNGage, a deeptech startup developing a new generation of high-performance MEMS sensors. He holds a PhD in Microtechnologies and began his career at the startup SILMAG, developing advanced magnetic sensor technologies for data storage, before joining THALES to work on high-end MEMS inertial sensors for aerospace and defense applications.
He joined CEA-Leti in 2001, where he held successive leadership roles, including Head of the MEMS Sensors Laboratory and Head of the Microsystems Department (120+ people), before leading Business Development for Microsystems.
In 2025, he founded iNGage as CEO & CTO, leading corporate strategy, fundraising, and execution.
He has authored over 50 scientific publications and holds more than 60 patents, including more than 20 related to the M&NEMS architecture at the core of iNGage’s innovation.
Bruno Vazzoler
Executive VP - Strategy, Innovation & Technology, Safran Electronics & Defense
Bruno Vazzoler
Executive VP - Strategy, Innovation & Technology, Safran Electronics & Defense
Bio:
Bruno Vazzoler started his career in 1989 within the Thales Group where he has held various positions in the fields of on-board radars, avionics equipment, land surveillance radars and rail systems.
In 2010, Bruno joined Segula Technologies as President of SIMRA and in 2014 he became General Manager and Executive VP of the Electrical Systems and Cockpit Solutions Division (DECS) of Zodiac Aerospace Group.
From 2019 to 2024, Bruno served as Executive VP of the Avionics Division at Safran Electronics & Defense.
Since 2024, he has held the position of Executive VP of Strategy, Innovation & Technology of Safran Electronics & Defense.
Bruno Vazzoler graduated from Ecole Polytechnique (1984) and Ecole des Ponts et Chaussées (1989).
Pierre-François Louvigné
CEA, SilMach
Pierre-François Louvigné
CEA, SilMach
Bio:
Trained as a physicist, with advanced degrees in Materials Science and Engineering and an MBA, Pierre-François Louvigné spent 23 years at the French Defense Procurement Agency (DGA), where he held various roles related to innovation and defense programs. Concurrently, he managed a family-owned SME in Paris for 13 years. In 2001, he became the go-to "National titanium expert," advising ministries and major industrial groups on public policy and procurement strategy for this strategic, high-tech metal, a role he maintained until 2021. He joined SilMach in 2015 as Sales Director to expand the company’s business and drive its industrial transformation. In 2021, he was appointed CEO.
Cybersecurity
Marion Andrillat
Cybersecurity Strategic Partnership Manager, CEA-Leti
Marion Andrillat
Cybersecurity Strategic Partnership Manager, CEA-Leti
After a Microelectronics Engineer degree at CPE Lyon, Marion Andrillat has started her career at STMicroelectronics as a digital designer of “System On Chip” for the payed TV setup boxes and consumer smartphones. In 2011, with a postgraduate Advanced Master in Marketing and Technological Innovation at Grenoble Ecole de Management, she joined the CEA as Strategic Marketing Manager. Then she moved as Strategic Partnership Manager for Systems Division at CEA Leti. Since 6 years, she is specialized in Cybersecurity Strategic Partnership Management for a wide range of industrial applications such as transports, smart grids, medical, industry 4.0, security & defense… and various devices such as integrated circuits, embedded systems or industrial equipment’s.
Mikael Carmona
Head of Cybersecurity Department, CEA-Leti
Mikael Carmona
Head of Cybersecurity Department, CEA-Leti
BIO:
Mikael Carmona is an engineer (Grenoble INP, 2007), agrégé in mathematics (2007), and PhD in signal processing (Grenoble INP, 2011). Researcher at CEA-Leti from 2011 to 2015 in the field of sensor networks, he co-founded the start-up Morphosense as CTO. He mainly contributes to the establishment and execution of the company's Technological, Product and Operational roadmaps. In 2021, he joined the Cybersecurity department of CEA-Leti and worked in the fields of post-quantum cryptography and random number generators. He took charge of the Component Security Laboratory from 2022 to 2025. He is currently Head of the Cybersecurity department of CEA-Leti
Abstract:
Technological transition can have huge impacts on hardware security of embedded devices. The examples are multiple. Post-quantum transition implies the modification of harware accelerators and countermeasures against physical attacks. RISC-V processors allow new approaches for securing components. Transistor technology migration change the properties of random number generators and the resilience to physical attacks. In that presentation, we present VASCO a serial of ASIC testing vehicles allowing implementation, physical modeling and security testing regarding cybersecurty standards of the main technological transitions.
Xavier Banchelin
R&D and Product Management Director, Thales
Xavier Banchelin
R&D and Product Management Director, Thales
Bio:
Xavier Banchelin is currently R&D and Product Management Director in the Identity & Biometric Solution Business Line of Thales, where he drives the development and product management of chip enabled solutions for identity documents.
As R&D professional with an in-depth experience of smartcard related technologies Xavier joined Thales 28 years ago and has held various engineering positions in France and in Singapore, contributing to the deployment of several new key technologies such as Javacards(TM) or electronic passports.
Xavier is a Graduate Engineer from Centrale Méditerranée.
Abstract:
Over the last two decades, electronic identity documents encountered a tremendous development. This is now a mature ecosystem with clear rules as it comes to regulations, standardisations and cybersecurity certifications. The presentation will detail how the integration of Post Quantum Cryptography is triggering changes to this framework.
Nathalie Feyt
VP Product Security, Cyber Center Of Excellence, Energy Management, Schneider Electric
Nathalie Feyt
VP Product Security, Cyber Center Of Excellence, Energy Management, Schneider Electric
Bio:
Nathalie Feyt joined Schneider Electric in 2025 as Vice President of Product Security, Cyber Center Of Excellence for the Energy division. As recognized leader in cybersecurity and digital transformation, she defines strategic technology directions for a wide range of Schneider Electric offers, from medium-voltage breakers to data centers and smart buildings.
In 2026, she spearheads the CEA–Schneider joint research lab for a 3-year renewal, advancing collaborative R&D She previously spent 18 years at Thales as Director of Cybersecurity in both the avionics as Chief Product Security Officer and in governmental sectors, as Thales ITSEF Director under ANSSI mandate. Her early career at Gemalto’s cybersecurity lab led to multiple patents and international publications.
Abstract:
Explore how a Responsible AI governance framework, grounded in cybersecurity controls, can accelerate innovation rather than constrain it. This session walks through the progression from enterprise-level AI oversight to proof-of-concept development, and ultimately to operational deployment of a use case. It demonstrates how to move from theory to practical industrial intelligence by using governance and cyber requirements as the foundation.
Bernard Vian
General Manager, SEALSQ France
Bernard Vian
General Manager, SEALSQ France
Bio:
Bernard Vian serves as General Manager of SEALSQ France. Before its acquisition by the group WISeKey, Mr. Vian served as the Executive Vice President of the Secure Transaction Business Division, Vice President of Business Development and Executive Vice President for Secure Payments at INSIDE Secure SA. He came to INSIDE Secure from Gemplus where he served in several positions in Sales Support and Marketing, in Europe and lately in California where he opened the Gemplus North America headquarter and served as Technical Support Director for 5 years. Mr. Vian joined INSIDE Secure's team in 2002 as Business Development Vice President. He is a graduate of the University of Aix-Marseille, France, with an engineering degree in Electronic Systems.
Julien Airaud
Senior Expert in Space Cybersecurity, CNES
Julien Airaud
Senior Expert in Space Cybersecurity, CNES
Bio:
Julien Airaud is a Senior Expert in Space Cybersecurity with over 20 years of experience in protecting critical systems and products. Specializing in the convergence of space and cybersecurity strategies and technologies, he focuses on enhancing organizational and technical resilience while ensuring operational continuity.
Julien has a proven track record of managing budgets exceeding €20 million and leading multidisciplinary teams. He excels in designing comprehensive security strategies, spanning cyber governance, protection, operational threat detection, and response mechanisms.
His previous roles include operational security for a banking institution, EMEAR infrastructure management for an international manufacturing group, infrastructure architecture for another industrial enterprise, and security analysis for an insurance company.
A frequent speaker at conferences and an active contributor to various cybersecurity and space groups.
Ahmadou Sere
Head of the Cyberdefense Department, ENEDIS
Ahmadou Sere
Head of the Cyberdefense Department, ENEDIS
Bio:
Ahmadou SERE is Head of Cyber Defense at a major European energy distribution company, where he leads large-scale security operations across critical infrastructure, including SOC, CSIRT, threat intelligence, and offensive security.
With a background in computer engineering, he specializes in navigating the growing complexity between operational cybersecurity, industrial constraints, and evolving regulatory frameworks such as NIS2 and European cyber resilience requirements.
His work focuses on scaling cyber defense capabilities in real-world environments, where technological ambition must align with operational reality, risk exposure, and regulatory pressure.
He brings an industrial perspective on how organizations adapt their security posture to meet both technological and compliance-driven transformations.
Marc Peresse
Cybersecurity Expert Leader, Renault Group
Marc Peresse
Cybersecurity Expert Leader, Renault Group
Bio:
Marc Péresse works within Ampere Software Technology, where he contributes to the definition and security of next‑generation vehicle software platforms. With over 25 years of experience in embedded software architecture, cybersecurity, and critical systems, he has built an international career spanning semiconductors, telecommunications, and the automotive industry.
After holding positions at Intel (France and the United States) as a security architect and embedded software engineering manager, he joined Renault, where he successively led transverse software architecture, vehicle cybersecurity, and high‑performance compute units. He is now a key reference on Software Defined Vehicle cybersecurity, in close alignment with international standards and regulations.
Marc is a graduate of Grenoble INP – ENSERG.
Sébastien Lasserre
Product Marketing Manager FD-SOI Business Line, Soitec
Sébastien Lasserre
Product Marketing Manager FD-SOI Business Line, Soitec
Bio:
FD-SOI Product Marketing Manager | Semiconductor Industry Expert
With 25+ years of experience in semiconductors, Sébastien’s expertise spans from 0.25µm down to 7nm FinFET nodes across R&D and manufacturing. His career is marked by technical leadership in process engineering, yield enhancement, device development (eDRAM cell, RF, CMOS High Voltage, …) and 14nm FDSOI technology assurance implementation. Having held pivotal roles at industry leaders like Siemens, Infineon, and IBM, he has a proven track record of navigating complex international alliances partnering with UMC, NXP and ST Microelectronics.
Since joining Soitec in 2018, Sébastien has been instrumental in the global growth of FD-SOI. Combining a Master’s in Physics with an Engineering degree in Opto and Micro-electronics from French National Engineering School in Caen, he now leverages his deep technical roots and know how in advanced substrate to drive product marketing strategy and innovation around FD-SOI engineered substrate.
Raphaël Collado
Head of Security Testing and Tools Laboratory, CEA-Leti
Raphaël Collado
Head of Security Testing and Tools Laboratory, CEA-Leti
Bio:
With nearly 20 years of experience in the R&D departments of consumer electronics companies, I have been a member of the cybersecurity team at CEA LETI for the past seven years. I started as a research engineer and have since led the Laboratory of Security Tests and Tools (LTSO) for the past five years.
Throughout the first 20 years of my career, I have worked at several companies, holding various positions ranging from embedded software developer to team leader, including roles as a software architect.
My areas of interest cover all aspects of cybersecurity for electronic devices, encompassing both hardware and software.
I hold a master's degree in mathematics and computer science (university of Savoie), as well as a master's degree in management (CNAM Paris).
Abstract:
The activities of the LTSO laboratory at CEA/LETI focus on the research and development of new testing techniques and tools to evaluate the cybersecurity of electronic devices. This includes both hardware and embedded software components, with a holistic view of the systems. A major key aspect to enhancing the security of these systems is the identification of vulnerabilities to anticipate and address potential fixes.
This presentation will showcase the tools developed at LTSO, with a particular focus on how they can aid in evaluating compliance with new regulatory requirements such as the CRA, as well as enhancing the resilience of systems against sophisticated attacks.
The FAMES Pilot Line
Dominique Noguet
FAMES Pilot Line Project Coordinator, CEA-Leti
Dominique Noguet
FAMES Pilot Line Project Coordinator, CEA-Leti
Bio:
Dominique Noguet holds an engineering degree of the National Institute of Applied Sciences (INSA) in electrical engineering in 1992, and a PhD from National Polytechnical Institute of Grenoble (INPG) in 1998. Then, he held several positions at CEA-Leti as a digital IC designer, lab manager and department manager. He led many projects at a national level and in several European frameworks (FP5, FP6, FP7). In January 2023, he was appointed project manager for the France 2030 flagship project NextGen. He is currently the coordinator of the FAMES Pilot Line and reports to CEA-Leti’s CEO. Dominique is a CEA senior expert and an IEEE Senior Member. He has authored or co-authored ~100 scientific papers (several best paper awards), several book chapters and 15 patents. He was a reviewer and a member of scientific committees of many conferences and a member of journal editorial boards. He was conference chair and TPC chair of several international conferences.
Abstract:
The FAMES pilot line has reached a pivotal stage, with highly innovative results obtained on all developed technologies.
These outcomes enable to strengthen FAMES partnerships and further feed other FAMES key initiatives, such as our
open-access and training programs. Moreover, the official inauguration of the Pilot Line earlier this year, was marked by the
launch of a state-of-the-art cleanroom, which is a major asset of the Pilot Line implementation strategy.
Susana Bonnetier
FAMES Pilot Line Open Access Chairperson, CEA-Leti
Susana Bonnetier
FAMES Pilot Line Open Access Chairperson, CEA-Leti
Bio:
Susana Bonnetier is a member of the FAMES Pilot Line management team and leads the Open Access effort with the goal of making « European-grown » advanced semiconductor technologies readily accessible to industry and academia.
An MIT engineer with a background in industry and research in the USA and France, Susana puts all her energy into transferring technological innovation to companies.
Born in Venezuela, Susana spent 9 years in the USA, where she completed her higher education and worked for General Electric Aircraft Engines, designing and building aircraft engines.
In 1991, Susana joined Saint-Gobain in France, first in the Industrial Strategy and Planning department working with 20 manufacturing plants to streamline and modernize their operations, and then at Saint-Gobain Cristaux et Détecteurs as Product and Industrial Market Manager, significantly increasing the profitability of a scintillation detectors product line.
In 2001, she moved to Grenoble, “the land of nano and micro technologies”, and reoriented her career towards the semiconductor industry. She joined Freescale as R&D Engineer and contributed to the successful development of the 65nm and 45nm CMOS technology nodes by the Crolles 2 Alliance.
In 2007, Susana joined CEA-Leti, first as head of a joint laboratory between Leti and a major French optics company, and later as Leti’s Carnot program manager, piloting a 14M€ R&D budget within Leti’s Scientific Directorate. During that time, she was VP of the Carnot Network and a member of its board of directors.
Susana brings a solid industrial and R&D experience to the FAMES Pilot Line project and the aim of contributing to the construction, in concert with the FAMES European Partners and the complementary Chips Act Pilot Lines, of a pan-European semiconductor ecosystem with the best Europe has to offer in microelectronics technologies.
Abstract:
The open-access concept of the FAMES pilot line project continues to be a key annual meeting point.This presentation will assess the responses to the 2025 call for proposals, introduce newly opened topics for 2026, and outline participation pathways. It will also feature a dedicated focus on the availibility of pathfinding design kit to evaluate the performance of the 10nm FD-SOI CMOS technology.
Laurent Fesquet
Deputy DIrector of the TIMA Laboratory (UGA - Grenoble INP - CNRS)
Laurent Fesquet
Deputy DIrector of the TIMA Laboratory (UGA - Grenoble INP - CNRS)
Bio:
Laurent FESQUET received the Ph.D. degree in electrical engineering from
Paul Sabatier University, Toulouse, France, in 1997. In 1999, he joined the Grenoble Institute of Technology, Grenoble, France, as an Associate Professor at ENSERG (now PHELMA).
His current research at the TIMA Laboratory today covers asynchronous circuit design, computer-aided design (CAD) for event-based systems and non uniform signal processing. He has served as general and program chair of several international conferences. He is currently the Deputy Director of the TIMA laboratory and CIME Nanotech, an academic center supporting microelectronic teaching and research activities
Claire Fenouillet-Beranger
Project Manager, CEA-Leti
Claire Fenouillet-Beranger
Project Manager, CEA-Leti
Bio:
Claire Fenouillet-Béranger joined CEA-Leti, Grenoble, in 1998 where she carried out her PhD. work on the integration and characterization of SOI devices. From 2001 to 2013 she worked as a CEA-Leti assignee in advanced R&D STMicroelectronics center, Crolles, France on FD-SOI (Fully-depleted SOI) technology platform development and characterization. From 2013 to 2020 she worked as the project leader of the low temperature MOSFETs development for 3D sequential integration. From January 2020 to January 2022, she was the LETI SiC pilot line project manager in the frame of the joint development program between SOITEC & AMAT. She is the author and co-author of more than 200 publications in major conferences and journals and of more than 40 patents. She was the co-recipient of the Grand Prix du Général Ferrié in 2012 for her work on FD-SOI. She is in charge of CMOS patent portfolio. Since 2022, she is director of research, and CEA Fellow expert, and co-project manager of the FD-SOI next generation node integration at CEA-Leti.
Abstract:
In the context of 10 nm FD-SOI technology development, new architectural and process building blocks must be implemented to meet the targeted device performance specifications. Strain engineering remains one of the primary performance boosters. Strain can be introduced either at the wafer level or at the device level. Additional process modules are required to further reduce access resistance and enhance overall device performance. In particular, the integration of in-situ doped, faceted raised source and drain regions is critical. Achieving the aggressive contacted poly pitch (CPP) target of 68 nm necessitates the implementation of advanced patterning techniques, specifically Self-Aligned Double Patterning (SADP), to meet density scaling requirements. In this presentation, we’ll dive into each of these levers and explore how they can push FD-SOI to the next level.
Laurent Grenouillet
Integration and Device Engineer - Ferroelectric Memory Group Leader, CEA-Leti
Laurent Grenouillet
Integration and Device Engineer - Ferroelectric Memory Group Leader, CEA-Leti
Bio:
Laurent Grenouillet received the Engineer degree in physics in 1998 from the National Institute of Applied Sciences (INSA) in Lyon, France, and the PhD degree in electronic devices in 2001. From 2001 to 2009 he worked at CEA-Leti on Optoelectronics and Silicon Photonics. In 2009, he joined IBM Alliance in Albany, USA to contribute to the development of FDSOI technology and took part to the FDSOI technology transfer to Global Foundries (22FDX) in 2015. Back in France, he joined the Advanced Memory Device Laboratory at CEA-Leti where he worked on resistive switching memory devices. In 2018 he started to work on ferroelectric HfO2-based memories (FeCaps, FeRAM, FTJs) and he is now leading the Ferroelectric Memory group at CEA-Leti.
Abstract:
CEA-Leti research engineers have demonstrated for the first time a scalable Hf0.5Zr0.5O2 (HZO) based ferroelectric capacitor platform integrated into the back-end-of-line (BEOL) at the 22nm FD-SOI technology node. This breakthrough represents a major milestone in ferroelectric memory technology, significantly advancing scalability for embedded applications and positioning ferroelectric RAM (FeRAM) as a competitive memory solution for advanced nodes.
This demonstration opens the door to faster, more energy-efficient, and cost-effective memory solutions in embedded systems such as IoT, mobile devices, and edge computing, and further strengthening Europes's position in both the FD-SOI and the FeRAM Technologies.
Marie Bousquet
Project Manager, CEA-Leti
Marie Bousquet
Project Manager, CEA-Leti
Bio:
Marie Bousquet is a Research Engineer at CEA-LETI, Grenoble, France. She received M.S. and PhD degrees in materials science from the University of Limoges, France, in 2007 and 2010, respectively. After 6 years of academic and industrial experiences, she joined the CEA-LETI, Grenoble, France where her interest is on the integration of piezoelectric materials (LiNbO3 and LiTaO3) in RF acoustic devices (SAW, BAW, Lamb) and management of industrial and academic R&D projects. She has authored and co-authored more than 40 scientific journal and conference papers and contributed to 10 patents on RF acoustic devices.
Abstract:
The FR3 range, from 7.125 to 24.25 GHz, is expected to extend by exploiting an intermediate region between the sub-6 GHz and the millimetric range. Filtering solutions based on Bulk Acoustic Wave (BAW) filters have to adapted for this frequency range. In this talk, we will present the main challenges (design, co-integration, process control, wafer level packaging, and so on) related to the up-scaling of BAW technologies for this frequency range. This will be exemplified by preliminary results based on AlScN and LiNbO3 BAW devices for this frequency
Tuomas Pensala
Principal Scientist—MEMS Team, VTT
Sandrine Catrou
VP Marketing and Strategic Partnership, CEA-Leti
Sandrine Catrou
VP Marketing and Strategic Partnership, CEA-Leti
Bio:
Sandrine Catrou holds an Electrical Engineering degree and a Master degree in microelectronics both obtained in Bordeaux, France, in 1991.
She spent her first 15 years in chips design, alternatively at European Silicon Structures, Rousset, France, ATMEL Corporation, and STMicroelectronics, Grenoble, France.
In 2011, she joined CEA Technology Transfer Office in Grenoble, France, supervising market studies in microelectronics. She got involved in the launch of a dozen CEA deeptech startups in France.
In 2015, she joined CEA-Leti CTO office as Strategic Marketing Manager to provide semiconductor market insights. In particular, she got involved in major national strategic investment plans in microelectronics.
In 2020, Sandrine started developing CEA-Leti international industrial partnerships with semiconductor industrial leaders. She got involved in the High Level Forum to foster international collaborations between innovative clusters. She also got involved in the development of technological collaborations between Grenoble Silicon Valley and the K-Belt.
Abstract:
Insights into the semiconductor and electronics industries will concentrate on the latest market and technology trends. This analysis will explore design opportunities unlocked by innovative semiconductor technologies, with a special emphasis on FD-SOI technology, covering its current adoption status and market outlook. Driven by the promising advantages of FD-SOI transistors—ideally suited for a wide range of next-generation electronic applications—a new industrial ecosystem has emerged, fostering increased design wins and accelerating technology adoption.
Piotr Wisniewski
Head of Intelligent Semiconductor Systems Division, CEZAMAT
Piotr Wisniewski
Head of Intelligent Semiconductor Systems Division, CEZAMAT
Bio:
In 2014, he received his MSc. Eng. degree in microelectronics, photonics, and nanotechnology, and in 2020, a Ph.D. degree in electrical engineering from Warsaw University of Technology (WUT). Currently is the Head of the Intelligent Semiconductor Systems Department (SEMINSYS) and an assistant professor at the Centre for Advanced Materials and Technologies CEZAMAT WUT, responsible for managing the department's semiconductor technology line and R&D activities. He has been actively involved in several national and international projects related to microelectronics and photonics as a researcher and principal investigator.
Abstract:
This presentation explores the design of cybersecurity-oriented applications leveraging FD SOI technology, with a particular focus on RRAM integration. The integration of RRAM further enhances system security by providing non-volatile, scalable memory suitable for secure key storage, physically unclonable functions, and in-memory security primitives. It enables robust, low-power, and cybersecurity architectures, making them highly attractive for next-generation secure IoT, embedded, and edge computing applications.
Jean-Frédéric Christmann
R&D Engineer, CEA-Leti
Jean-Frédéric Christmann
R&D Engineer, CEA-Leti
Bio:
Jean-Frédéric Christmann received the M.S and PhD degrees in Electronics from the Grenoble Institute of Technology in France in 2009 and 2013. Since 2009, he is a research engineer at the French Atomic Energy Commission (CEA). He first was with the Digital Circuits and Systems Department where he worked on mixed-signals systems modelling, multicore processor assembly and functional validation, low power microcontrollers architectures, asynchronous processors logical synthesis and physical implementation, and In-Memory Computing controllers. From 2018 to 2022, he has been the digital technical leader for a world-class mixed-signals pressure sensor design. Since 2022, he is with the Silicon Component Department where he works on standard cells design automation and advanced technologies benchmarking.
Abstract:
To evaluate the performance of the 10nm FD-SOI CMOS technology process, FAMES offers a pathfinding design platform targeting both analog and digital design. Offering multiple devices, the compehensive PDK featuring DRC, LVS, PEX and Virtuoso support allows exploration of advanced process features. Moreover, 50+ combinational and sequential cells are derived in 16 standard cells libraries with Verilog, Spice, Liberty, and LEF descriptions, which enables the implementation of complex digital architectures and hence system-level benchmarking.
Régis Hamelin
CTO / aCCCEss coordinator, Blumorpho
Régis Hamelin
CTO / aCCCEss coordinator, Blumorpho
Bio:
Régis Hamelin earned an engineering degree in materials science and a PhD in Electronics from the University of Lille, where he researched semiconductor lasers with the IEMN optronics team in 1993. He spent seven years at CEA-LETI as a process engineer and program manager in optronics, developing expertise in compound semiconductor photonic components and packaging. In 2003, he co-founded Intexys Photonics, serving as CTO and board member in launching active optical cables for high-end supercomputers. In 2010, he joined the “COWIN” support action under FP7, leading to the foundation of BLUMORPHO, which he joined as CTO in January 2015. As BLUMORPHO’s Chief Technology Officer, he directs deep-tech innovation and helps European ecosystems advance in semiconductors, IP generation, and technology transfer.
He is currently coordinator of the aCCCess CSA coordinating the Competence Centers Activity.
Sana Ibrahim
Research Engineer in Microelectronics Design, Grenoble INP
Sana Ibrahim
Research Engineer in Microelectronics Design, Grenoble INP
Bio :
Sana Ibrahim received the M.S. degree in Wireless Integrated Circuits and Systems from Grenoble Alpes University (UGA), Grenoble, France, in 2020, and the Ph.D. degree in Nanoelectronics and Nanotechnologies from TIMA Laboratory, UGA, Grenoble, France, in 2024. In 2025, she joined Grenoble Institute of Technology (INP), Grenoble, France, as a research engineer at Phelma within the European project FAMES. During her doctoral studies, her research focused on the design of a wideband, low-power RF front-end based on N-path mixers in 28nm FD-SOI technology.
Her current work involves on developing and contributing to a comprehensive curriculum covering both analog/RF and digital design flows, aimed to provide designers with the foundational knowledge needed to develop integrated circuits using FD-SOI technology.
The RESOLVE Initiative
Bruno Paing
VP Europe & International Public Affairs, CEA-Leti
Bruno Paing
VP Europe & International Public Affairs, CEA-Leti
Bio:
Mr Paing has a substantial international (15 years abroad) and mixed public/private experience in private companies (Orange, Sagemcom), in the French Ministry of Foreign Affairs (scientific attaché in Taiwan in 1998-1999 and in Hanoi, Vietnam from 2002 to 2005) and in CEA since 2005.
He first promoted MINATEC innovation campus in Grenoble and then became CEA-Leti VP Industrial Partnerships to develop R&D programs with Industry. He also developed R&D partnerships with Japanese and American companies in Tokyo and California (Caltech, Pasadena) from 2013 to 2021, and then became International Relations Deputy Director at CEA Head Office in Paris-Saclay from 2021 to 2023. He now serves as CEA-Leti VP Europe & International Public Affairs in Grenoble.
Mr Paing is graduated from the French “CentraleSupelec” Engineering School (Master of Science in Engineering), from Lyon Business School / EM Lyon (Executive MBA), and he is an auditor of CHEAD (French Diplomatic Academy) in 2025.
Anne Van den Bosch
Vice President Public R&D Policies & Programmes, Imec
Anne Van den Bosch
Vice President Public R&D Policies & Programmes, Imec
Bio:
Anne Van den Bosch obtained her PhD degree at the Catholic University of Leuven in 2003 in the area of current steering digital-to-analog converters. She is the first author of 17 publications and the co-author of 5 publications. From 2001 until 2008, she worked for the Flemish funding agency, where she headed the micro-electronics and photonics team and represented the agency in the MEDEA+/CATRENE and ENIAC public authorities board. She is now working at imec as Vice-President Public R&D Policies and Programs and leads all imec activities related to Flemish, European and international public research policy and funding programs. She is also responsible for the contractual collaborations with international universities and research institutes. Since the beginning of 2023, she is executive Vice-President of the European Association of Space Technology Research Organizations. She is a member of several boards, management commissions, and steering committees.
Patrick Bressler
Director for International Cooperation, Fraunhofer Microelectronics Group
Patrick Bressler
Director for International Cooperation, Fraunhofer Microelectronics Group
Bio:
Dr. Patrick Bressler is the director for international cooperation, emerging technologies and innovation at the Fraunhofer Microelectronics Group / FMD (Research Fab Microelectronics Germany) in Berlin, Germany. Responsibilities include technology evaluation, developing partnerships for research, innovation and work force development, and advancing European and international R&D&I programmes. Patrick is a member of several European technology advisory boards and scientific committees. Since September 2024 Dr. Bressler also serves as the Secretary General of the European Materials Research Society, E-MRS.
Patrick is a physicist by training. Earlier career stages include:
Managing Director of the Fraunhofer Microelectronics Office in Berlin, Germany,
Executive Vice President of Fraunhofer USA, in charge of research operations at the seven Fraunhofer R&D centers, Plymouth, MI, USA,
Adjunct professor at Michigan State University, East Lansing, MI, USA,
Director of Fraunhofer Brussels, Brussels, Belgium,
Head of Unit for Physical Sciences and Engineering of the European Science Foundation, Strasbourg, France (2004-2008),
Member of the E-MRS Governing Board (2005-2015) and Chairman of the European Materials Science and Engineering Expert Committee (MatSEEC, 2012-2015) and Senior scientist and Head of Unit at the Berlin Synchrotron BESSY, Berlin, Germany.
Sven Beyer
Technology Architect, Global Foundries
Sven Beyer
Technology Architect, Global Foundries
Bio:
Sven Beyer received his master’s and Ph.D. in Physics from the University of Hamburg, Germany. He started his career with Infineon as a manufacturing engineer in the etch department in 2003. Joining the integration department of AMD in 2005, he intermediately spent a year in the IBM ASTA alliance 2007 working on the 45nm node. Returning to Dresden, Sven has worked in many roles since then, ranging from integration technology-lead to customer engineering and lasting throughout the separation of GlobalFoundries and AMD. Today he serves as DMTS in GlobalFoundries FAB1 as technology architect (TA), overseeing mainly the eNVM & CMOS roadmap and development in Dresden.
Abstract:
Introducing the “AI stack” at the example of transformer-based AI and laying out current and potential future ownership of the elements of this stack, I will make the daring claim that “Attention ain’t everything”. Hence, pushing the digital brute force computing capability of leading-edge CMOS alone, by continuing to stumble along the path of Moore’s law, will likely never deliver true human like intelligence. Perusing this way, striving for true human like intelligence, power consumption will sky-rocket, eventually building an insurmountable barrier. It will need another paradigm shift, already foreseeable at the horizon, to lift AI capabilities on a manageable power budget, to the next level. Here the value-added solution (VAS) device offerings of mature CMOS nodes, like non-volatile memory cells, in combination with specialized low power CMOS platforms, might play a crucial role. In addition, financially affordable CMOS technologies bear the chance to bring this fascinating technology into the edge devices.
Startups & Investments
Sylvain Colomb
Startup Program Manager, CEA-Leti
Sylvain Colomb
Startup Program Manager, CEA-Leti
Bio:
Sylvain Colomb began his career as a Marketing Engineer within CEA’s technology transfer division, where he spent eight years supporting laboratories and emerging startups. In 2010, he co-founded Ethera, a startup specializing in indoor air quality fueled by disruptive nanomaterial technology. After successfully scaling the company and its integration into the SEB Group, he returned to the innovation ecosystem. Since 2019, Sylvain has served as the Startup Program Manager at CEA-Leti, where he currently leads entrepreneurship initiatives and spearheads strategic support for new startup creation from CEA-Leti's laboratories.
Laurence Petit
Director for Innovation, CEA
Laurence Petit
Director for Innovation, CEA
Bio:
Laurence Petit is a graduate engineer (MSc) from the École Nationale Supérieure de Chimie de Paris (Chimie Paristech). She also holds a PhD in quantum chemistry from the University of Grenoble. She has been certified as a Project Management Professional by the PMI since 2015.
She began her career in 2007 at the École Normale Supérieure de Lyon, where she completed a one-year postdoctoral fellowship for TOTAL.
From 2008 to 2019, Laurence Petit worked at the French National Agency for Radioactive Waste Management (Andra). She first worked in R&D, and in 2010 she took charge of managing Andra’s “Investissements d’Avenir” (Investing in the Future) programme (€75M), a position she held until 2019. Starting in 2016, she became Head of Innovation at Andra, and in 2019 she was appointed Deputy Director of Development, Innovation, and International Relations Division.
Laurence Petit joined CEA at the end of 2019 as Technical Innovation Advisor to the Chairman and CEO, François Jacq, a role she held until the end of 2021. She has been Director for Innovation at CEA since 2022. She is specifically responsible for the strategic and operational management of all CEA's start-up support programs (10 to 15 spinoff creations each year) and for managing CEA Investissement subsidiary.
Régis Saleur
Managing Partner, Supernova Invest
Régis Saleur
Managing Partner, Supernova Invest
Bio:
Régis has been part of the team since 2008 as Managing Partner. He has more than 25 years of experience in private equity and operations.
From 2003 to 2007, he was general partner at Galileo, where he invested in Talend (software publisher, 500 employees, Nasdaq: TLND), Alyotech (engineering and technology consulting, 1,900 employees), and Sarenza (online sales, 300 employees). Régis was Managing Director of Seeft Ventures from 1999 to 2003 (digital start-up management). He is a graduate of École Centrale Paris. Régis is on the boards of Aledia, Aveni, Kalray, Aselta, Crocus, Prophesee.
Pierre Garnier
Managing Partner, Jolt Capital
Pierre Garnier
Managing Partner, Jolt Capital
Bio:
Pierre Garnier has over 30 years of operational and C-suite experience across large corporates and scale-ups, in sectors such as semiconductors, hardware, software and cybersecurity. Prior to joining Jolt Capital, Pierre was most recently President of e2v-semiconductor, a leader in the semiconductor market for aerospace & defence where he accelerated growth of 15% in less than a year before its sale to the Teledyne Group in 2017.
Preceding this, Pierre served as COO of Inside Secure (EUR: INSD) where he led its transformation from a semiconductor player into an embedded software security leader. Pierre has also held various other top executive roles including VP & General Manager of the Wireless BaseBand Business Unit at Texas Instruments (TI), CEO at Everbee Networks, and General Manager of the Broadband Chipset Business Unit at Alcatel Microelectronics (now part of ST-Microelectronics). Pierre holds an Engineering degree from École Supérieure d’Électricité (Supélec), and a Master of Solid State Physics from UPMC (Pierre and Marie Curie University).
Pierre is currently on the boards of Interel, MicroOled, Dolphin Semiconductor and P2i, as well as an observer on the boards of EfficientIP and Tehtris. Pierre led the exit process of UnitySC to Merck (ETR:MRK).
Steven Konsek
Investment Director, Applied Ventures
Steven Konsek
Investment Director, Applied Ventures
Bio:
Steven Konsek is an Investment Director at Applied Ventures where he focuses on photonics and displays in addition to supporting investments and startup ecosystem engagement in Europe and Israel.
Prior to joining Applied Ventures in 2022, Steven spent nearly two decades working with and funding deep-tech startups in the U.S. and Europe. He was most recently Director of Business Development at Aledia, a French photonics startup. Prior to Aledia, Steven led innovation programs at the U.S. National Science Foundation, where he ran NSF’s portfolio funding startups in the semiconductor, photonics, advanced materials, and IoT sectors as well as leading the Innovation Corps program for deep-tech startups. Prior to NSF, Steven held leadership positions in several semiconductor/photonics startups, including Illumitex, Glo/Qunano, and Nantero.
Steven has a PhD in Physics from the University of Washington and BS in Mathematics from Purdue University. He is based in Geneva, Switzerland.
Bernard Aspar
Silian Partners / Ardian Semiconductor
Bernard Aspar
Silian Partners / Ardian Semiconductor
Bio:
Bernard Aspar, Partner of Silian Partners, contributes over 30 years of industry experience and is a recognized world expert in semiconductor materials. He entered Silian Partners coming from his COO position at Soitec which he joined in 2006 during the acquisition of Tracit Technologies, a company he founded in 2003. Tracit Technologies was a spin-off of CEA-Leti, where he spent 10 years in semiconductor research.
Thomas Ferré
Private Equity Investor, EIC/EIB
Thomas Ferré
Private Equity Investor, EIC/EIB
Bio:
Thomas is a private equity investor with nearly 20 years of investing in companies across the world. Today he works at the European Investment Bank for one of the EU's largest venture fund with EUR 3.7bn, the EIC Fund, where he specializes in venture and growth investments in AI, semiconductors and quantum computing across Europe. He is a former award winning circular economy entrepreneur and an engineering graduate of the Arts et Metiers ParisTech and the University of Michigan.
Shaping What’s Next
Michael Tchagaspanian
EVP Strategic Partnership, CEA-Leti
Michael Tchagaspanian
EVP Strategic Partnership, CEA-Leti
François Legrand
Communication Manager, IRT Nanoelec
Makoto Motoyoshi
President & CEO, Tohoku-MicroTec
Makoto Motoyoshi
President & CEO, Tohoku-MicroTec
Bio:
Dr.Motoyoshi is the semiconductor expert with more than 25 years of experiences at technology and business in Memory device and 3D Stacking LSI. He is former President & CEO of ZyCube, Inc., the leading 3D Stacking LSI for CMOS image sensor in Japan. He has presented seminars, lectures and invited presentations at domestic and international societies associated with 3D Stacking LSI over 40 times.
1982: Master of Electronic Engineering,
Tohoku University, Japan
1982: Hitachi Ltd., Musashi Works
1989: Kawasaki Steel Corp, LSI Research Center
1992: Sony Corp, LSI div.
2005: ZyCube, Inc., Director of Engineering
2006: ZyCube, Inc., Executive vice president
2008: ZyCube, Inc., President & CEO
Swan Gerome
RF & Telecommunications Industrial Partnership Manager, CEA-Leti
Swan Gerome
RF & Telecommunications Industrial Partnership Manager, CEA-Leti
Bio:
Swan GEROME is Technology Partnership Manager within the Systems Department, with a focus on RF and Telecommunications at CEA-Leti.
He holds a degree in Marketing and Sales Management from Grenoble IAE and has over 15 years of experience in the semiconductor industry across materials, design, and research companies.
From 2008 to 2014, he served as Sales Manager at Dolphin Integration, developing business for ASIC design, analog silicon IP, and libraries for foundries, fabless companies, design houses, and OEMs. He also managed a team of sales coordinators in Asia (Japan, South Korea, and Taiwan) as well as in Europe.
He joined CEA-Leti in 2015 as Industrial Partnership Manager for the Systems Department, covering sensor integration, energy management, embedded data processing, and RF telecommunications (antenna design and integration, protocols development, and RFIC design). In this role, he developed partnerships with national and international companies, ranging from startups to Big Tech.
Between 2022 and 2023, he was Product Marketing Manager for the Connect-SOI Business Unit at Soitec, where he developed the roadmap for engineered silicon substrates for RF applications and launched new products to address market requirements.
Abstract:
Harnessing dielectric permittivity the property that describes how electric fields propagate through matter CEA‑Leti researchers have built a non‑invasive, chip‑scale technology that maps the hidden electrical signatures of cells and materials.
The device emits radio‑frequency from 30KHz to 30GHz, captures transmitted and reflected signals, and decodes them with a silicon‑integrated vector network analyzer (VNA). This yields an ultra‑miniaturized, low‑cost, low‑power, wide‑band system that can be embedded in portable and wearable devices.
This session will show how CEA-Leti enables non-invasive detection across multiple sectors, such as health care, wellness, agri-food, and automotive by converting dielectric permittivity maps into actionable insights. The technology unlocks a world of applications ranging from cancerous-cell detection, hydration monitoring, process monitoring, and proximity detection.
Vincent Destefanis
Optical Sensors Industrial Partnership Manager, CEA-Leti
Vincent Destefanis
Optical Sensors Industrial Partnership Manager, CEA-Leti
Bio:
Vincent Destefanis is a Partnership Manager for the Optics and Photonic division of CEA-Leti since 2023. Since 2006, he was successively a R&D engineer, a senior technical expert and a partnership manager, this for various leading-edge photonic and CMOS companies (Lynred, STMicroelectronics and IBM).
He holds Master's and Engineering degrees in Electronics, Physics and Materials Science. During his career, Vincent has been successful in creating long-term value in the CMOS and photonic industries, from various valuable contributions to industrial projects and partnerships.
Vincent is now dedicated to the development of industrial partnerships for the development and tech transfer to industry of beyond the state of the art photonic sensing solutions addressing a wide scope of applications.
Abstract:
Global demand for accurate non-invasive glucose monitoring remains unmet, because most wearable technologies fail to deliver the required clinical performance. CEA-Leti offers a device breakthrough with mid-infrared quantum cascade laser (QCL) photoacoustic technology on silicon. Operating in the mid-IR spectrum, it provides the specificity and sensitivity needed for real-time biomarker tracking without invasive sampling.
Engineered for large-scale semiconductor manufacturing, the system ensures cost-effectiveness and significant scalability. Its retunable architecture allows a single hardware design to detect diverse biomarkers across medical and industrial sectors. The institute aims to accelerate time-to-market through this multilateral industrial program.
This initiative reshapes non-invasive monitoring, enabling next-generation smart wearables like smartwatches for sport, wellness, and health. By translating this breakthrough into low-cost devices, CEA-Leti opens pathways for detecting crucial biomarkers and molecules beyond glucose, addressing global consumer demand, while overcoming previous technological limitations.
Marc Engel
CEO, Agileo Automation
Marc Engel
CEO, Agileo Automation
Bio:
Marc ENGEL is the CEO and Co-Founder of Agileo Automation, a French software company specializing in equipment control and connectivity for the semiconductor industry. With over 25 years of experience in industrial automation, Marc started his career as an engineer working on robotics and tool control at such OEMs as RECIF Technologies. As company CEO since 2010, he has led and driven the development of A²ECF-SEMI, a modular equipment automation framework used by OEMs worldwide to integrate SECS/GEM, GEM300, OPC UA, EDA, and Industry 4.0 capabilities.
At the intersection of automation and digital transformation, Marc has been involved in research and innovation projects supporting the adoption of digital twins, model-driven development, and edge-to-cloud architectures for production equipment. He also supports start-ups and established OEMs in defining automation strategies and implementing SECS/GEM interfaces for successful fab deployment.
Abstract:
As tier-one fabs move toward sub-ångström nodes and complex 3D AI chip architectures, legacy protocols can no longer handle the required data velocity. This session explores why Equipment Data Acquisition (EDA / Interface A) has evolved from an optional feature to a mandatory requirement for both standard front-end and advanced packaging OEMs. We will highlight the transition from SOAP-based Freeze 2 to the high-performance gRPC Freeze 3, enabling the "zero-defect" precision and high-frequency sensor modeling essential for modern yield. Attendees will learn how standardized data structures transform equipment into AI-ready assets, ensuring seamless integration into the data-driven ecosystems of 2026.
Laurent Pain
Sustainable Electronics Program Director, CEA-Leti
Laurent Pain
Sustainable Electronics Program Director, CEA-Leti
Bio:
Laurent Pain is graduated from the Ecole Nationale Supérieure de Physique de Grenoble in 1992. He received his Ph D after his work on DUV resists study. He joined CEA-Leti in 1996 to work on infra-red technology, and then came back to STmicroelectronics in 1999 working on 193nm and e-beam lithography technologies.
From 2008 to 2014, Laurent Pain leaded the lithography laboratory of the silicon technology division of CEA-Leti. He was also managing in parallel the industrial consortium IMAGINE dedicated to the development of multibeam lithography with MAPPER lithography BV.
Since July 2014, within the CEA-Leti Silicon Technology Division, he is now in charge of the business and the partnerships developments of the Silicon Technologies Platform Division.
Abstract:
The semiconductor industry underpins global digital transformation, with the ICT market expected to double by 2030 due to advances in AI, 5G, and cloud computing. A fundamental shift toward more resilient, sustainable, and circular manufacturing models is required to enable this growth. Key challenges include reducing water, gas, and metal consumption, minimizing PFAS dependence, and improving effluent circularity.
Attendees will hear how CEA-Leti’s comprehensive sustainability roadmap spanning the entire semiconductor value chain will integrate process innovation with system-level optimization to drive measurable environmental impact reduction. The SubFAB Labs initiative, developed in collaboration with International SubFAB Research Labs (ISRL), is a central pillar of the roadmap. This four-year program, which can be extended, will evaluate the subfab environment, from process to final waste treatment by improving material use, abatement strategy and global effluent? circularity. The aim is to reduce costs and global environmental impact.
Bastian Tröger
Director Product Marketing & Sales Support, Camtek Metrology
Bastian Tröger
Director Product Marketing & Sales Support, Camtek Metrology
Bio:
Bastian Tröger is the Director of Product Marketing and Sales Support for Camtek's Metrology product range.
As a graduate engineer specializing in physical optics, he brings many years of experience in optical metrology. He began his career at Camtek Metrology (then FRT GmbH) in 2007 within the development department, later established the company's product management department, and ultimately advanced into senior management.
Abstract:
The semiconductor packaging industry is accelerating beyond 2026, driven by AI, automotive, and data center demands. Advanced packaging - interposers, chiplets, and FOPLP - is becoming essential for higher performance and power efficiency.
Camtek's metrology solutions support this shift with a flexible, modular metrology platform (SurfaceSens) that covers the full range from R&D to HVM and from front- to back-end.
Key applications include thickness and shape measurement, CD/overlay control, RDL analysis, TSV depth/CD, RST, and large-field (nano)topography for CMP and hybrid bonding.
Adaptable handling enables full automation for all wafer sizes and panel-level processing—ideal for future FO-PLP production.
Vygintas Jankus
MicroLED Partnership Manager, CEA-Leti
Vygintas Jankus
MicroLED Partnership Manager, CEA-Leti
Bio:
Vygintas Jankus is responsible for industrial partnership for MicroLED & OLED technologies at CEA-Leti in Grenoble. He helps partners to develop these technologies for optical & data communication, AR/VR, automotive, and other applications.
Abstract:
This program on microLED datalinks addresses the bandwidth‑energy bottleneck limiting AI‑driven supercomputers. By scaling microLED optical links, the project targets sub‑1 pJ/bit energy use and >10.5 Tbps/mm data density over distances up to 10 meters, enabling point‑to‑point interconnects for CPUs, GPUs and HBM stacks.
Combining device, circuit and 3‑D integration expertise hybrid bonding and high‑density TSVs the consortium will manufacture microLEDs on 200 mm wafers using standard foundry technology, with a clear path to 300 mm scalability.
Why it matters: MicroLEDs offer a mature, low‑power alternative to copper or laser‑based interconnects that can deliver orders‑of‑magnitude speed gains, while sharply reducing power draw. Attendees will see the microLED-for-datacom roadmap, learn how the technology can accelerate AI workloads, lower data-center expenses, and open new opportunities for chipmakers, optical‑component suppliers and hyperscalers.
Optical Interconnects
Eléonore Hardy
Silicon Photonics Partnership Manager, CEA-Leti
Eléonore Hardy
Silicon Photonics Partnership Manager, CEA-Leti
Éléonore Hardy joined CEA-Leti in 2018 as a partnership manager specializing in silicon photonics. She holds a Master’s degree in Engineering and has completed a Master of Science in Management & Innovation. With over 20 years of experience in the optics and photonics industry, Éléonore has held key positions at Philips in the Netherlands and Varioptic, a business unit of Corning, in China.
Throughout her career, Éléonore has demonstrated a proven track record of creating long-term value. She successfully developed laser technologies in France, China, and India for Quantel (now Lumibird) and advanced spectrometer solutions in Europe and Asia for Resolution Spectra Systems (now part of Merck).
Currently, Éléonore is focused on identifying and developing new business opportunities in silicon photonics, with a particular emphasis on high-speed optical interconnects, high-performance computing (HPC), 3D sensing, and advanced computing technologies such as neuromorphic computing and quantum photonics.
Frédéric Hameau
Research Engineer & Project Manager, CEA-Leti
Frédéric Hameau
Research Engineer & Project Manager, CEA-Leti
Bio:
Frédéric Hameau received the M.S. degree from ENSEIRB, Bordeaux, France, in 2001. He joined CEA-LETI, Grenoble, France, as a radio-frequency research engineer. Over the past 23 years, he has contributed to the development of radio-frequency system-on-chip (SoC) technologies, covering ultra-low-power, ultra-wideband, and millimeter-wave applications. In this field, he is the author or coauthor of more than 28 conference papers, four IEEE journal articles, and 12 patents. He currently leads the optical-link activity within the CEA Radio-Frequency Laboratory, where he contributes to the development of application-specific integrated circuits (ASICs) for high-speed, low-power optical communications.
Sylvie Gellida
General Manager, Optical and RF Foundry Division, STMicroelectronics
Sylvie Gellida
General Manager, Optical and RF Foundry Division, STMicroelectronics
Bio:
Sylvie Gellida is STMicroelectronics’ General Manager, responsible for the Optical and RF Foundry Division, belonging to RF and Optical Communication product sub-group since January 2025.
Sylvie Gellida started her career as RF design engineer in Dolphin before joining ST Grenoble in 2000. In 2006, she joined the Foundry team as technical support and program manager, extended to marketing next, to sell ST differentiated RF silicon technologies. In 2021, she took the leadership of the mmW products Business Unit, as well as the RF technologies strategy position, encompassing the Silicon Photonics technology and business development from 2023. Since January 2025, Sylvie has been leading the Optical and RF Foundry Division, covering optical interconnects, LEO satellites communications and mmW markets.
Abstract:
Enabling energy-efficient data centers requires a fundamental shift from copper-based electrical links to high-bandwidth, low-loss optical connectivity. This talk will present ST’s silicon photonics strategy and the role of the PIC100 platform in replacing copper with integrated SiPho solutions for next-generation data center and AI interconnects. By combining differentiated Silicon Photonics, BiCMOS platforms in advanced packaging technologies, ST overcome the challenges of power efficient optical interconnects.
Patrick Le Maitre
Research Engineer, CEA-Leti
Patrick Le Maitre
Research Engineer, CEA-Leti
Bio:
Patrick Le Maitre received his engineering degree from CentraleSupélec in 2000 and a Master of Engineering from the Tokyo Institute of Technology in 2001. He began his career at Renesas Technology, where he focused on semiconductor design and development. He then joined NXP Semiconductors, contributing to RF transceiver design. In 2010, he moved to STMicroelectronics and worked on the development of a silicon photonics platform Since 2019, he has been a research engineer at CEA-LETI, specializing in the development of GaN-based emissive devices for microdisplay and optical communication applications.
Abstract:
We present a development pathway for short-range optical chip-to-chip communication using GaN-on-Si microLED and microPD arrays integrated with CMOS. The approach combines device and circuit optimization, hybrid bonding, and system modeling, enabling scalable, energy-efficient interconnects for next-generation computing architectures.
Francesco Manegatti
CO-founder & CEO, NcodiN
Francesco Manegatti
CO-founder & CEO, NcodiN
Bio:
Francesco is co-founder and CEO of NcodiN. He is a scientist, entrepreneur and innovator in the field of nanophotonics. With a PhD in optoelectronic nanodevices and over eight years of experience in cutting-edge photonics research, he has worked at the forefront of silicon photonics, optical memories, light amplification and III-V on silicon nanostructures. His journey has taken him through prestigious institutions such as CNRS, IBM, and C2N (Centre de Nanosciences et de Nanotechnologies), where he contributed to groundbreaking advancements in the field.
Originally trained as an electrical engineer, Francesco combined his technical expertise with a visionary approach to innovation. He has played a key role in developing ultra-small, high-efficiency lasers that are set to transform data processing and communication.
Passionate about pushing the limits of technology, Francesco is dedicated to solving some of the most pressing challenges in AI hardware and high-performance computing, enabling systems that are faster, more efficient and infinitely scalable.
Mohsen Asad
Senior Director, Core Technology, CREDO
Yvain Thonnart
Chief Scientist, Digital Integrated Circuits and Systems Division, CEA-List
Yvain Thonnart
Chief Scientist, Digital Integrated Circuits and Systems Division, CEA-List
Bio:
Yvain Thonnart graduated from Ecole Polytechnique and Telecom Paris, France in 2005. He then joined the Technological Research Division of CEA, the French French Alternative Energies and Atomic Energy Commission, within the CEA-Leti institute until 2019, then within the CEA-List institute.
He has led the development of several large research projects for on-chip communications, focusing on the maturation of novel concepts towards industrial adoption, such as communication between multiple voltage and frequency domains, 3D-stacked circuits, and optical on-chip interconnects.
He is now a CEA fellow, and chief scientist for the digital ICs and systems division of CEA-List.
Abstract:
Today's optical interconnects are largely limited to static, point-to-point links, with initialization and training times ranging from microseconds to milliseconds. While suitable for board-level or rack-scale communication, those latencies prevent optical links from being used as a true networking fabric inside multi-die packages. We address this gap by integrating optical switching, routing control and high-speed logic directly with silicon photonics. The result is a dynamically routed optical interconnect that operates at nanosecond timescales, enabling optical communication across centimeter-scale interposers with responsiveness previously limited to short electrical links.
Henri van Helleputte
Head of Business Development Europe and Unites States, ASML
Henri van Helleputte
Head of Business Development Europe and Unites States, ASML
Bio:
Henri is part of ASML’s Customer Team EU/US technology organization, focusing on technology strategy and business development for mainstream TWINSCAN lithography systems. In this role, he partners with customers across Europe and the United States on future technology roadmaps, application challenges, and operational requirements, working with the broader ASML organization to translate customer needs into improvements in products and services.
Since 2019, Henri has led business development for ASML’s dry TWINSCAN systems, building on earlier contributions across different business line —including significant growth in the 200 mm TWINSCAN business.
Prior to ASML, Henri spent 18 years at Philips in the Netherlands and the United States, holding management roles in Research, Design & Engineering, and Sales. He joined ASML in 2006 and has worked on PAS5500 and TWINSCAN platforms.
Henri obtained an MSc in Physics (Drs.) from Utrecht Rijks University (the Netherlands).
Mark Fuselier
SVP, Technology and Product Engineering, AMD
Mark Fuselier
SVP, Technology and Product Engineering, AMD
Bio:
Mark Fuselier is senior vice president of Technology and Product Engineering at AMD. He is responsible for silicon and packaging technology development and new product introduction engineering.
Fuselier has more than 29 years of semiconductor industry experience and has been involved in the development and production of process technology generations spanning from 35 micron through 2 nm across multiple fabs and product families. He played a central role in the development and productization of computing solutions such as 2 nm, multicore CPU and GPU SoC integration, heterogenous APUs, 2.5D and 3D chip packaging and chiplet System in Package (SiP) integration.
Fuselier holds a Master of Science degree in electrical engineering and Master of Business Administration from the University of Texas at Austin. He is a member of IEEE and the Electron Devices Society.
Disruptive Digital Interfaces
Philippe Caillol
Director of Innovation, CEA
Philippe Caillol
Director of Innovation, CEA
Bio:
Philippe Caillol is a professional in innovation and technological foresight with over 20 years of experience. After several years in the construction and media sectors within the Bouygues Group developing new products and services, he joined the CEA (A French Research and Technology Organisation) in 2012 to lead technology exploration teams. Since 2024, he has been the Director of Innovation within the CEA's Technological Research Division, where he oversees a team conducting multidisciplinary prospective studies and innovation projects exploring future uses of advanced technologies.
Laurent Filhol
Deputy Director of the Innovation Division, CEA
Laurent Filhol
Deputy Director of the Innovation Division, CEA
Bio:
Laurent FILHOL has been Deputy Director of the Innovation Division within the CEA's Technology Research Department for three years. Prior to this, he worked for various international companies in the field of information technology and data centers before joining the CEA in 2016 to work on IT and digital projects.
Johannes Zellner
Head of Roadmap Technology, ZEISS SMT
Johannes Zellner
Head of Roadmap Technology, ZEISS SMT
Bio:
Dr. Johannes Zellner is Head of Roadmap Technology at ZEISS Semiconductor Manufacturing Technology (SMT). Since joining ZEISS in 2002, he has progressed from optical design and simulation of lithography lenses to leadership roles across ZEISS, including Team Lead Optical Design (SMT), Director Design Engineering (SMT Laser Optics), Director System Design Illumination (SMT), and Director Systems Design (Consumer Products). In his current role (since 2024), he drives research, early technology development and strategic innovation programs and contributes to shaping the ZEISS SMT strategy. He holds a PhD in Physics from the Karlsruhe University (now KIT).
Abstract:
The acceleration of AI is redefining what semiconductor technologies must deliver, from scaling to system‑level integration. As computational architectures evolve, shaping and controlling light becomes increasingly central to enabling further progress. Advances in patterning, metrology, and integration are now essential not only for continued density gains but also for supporting new three‑dimensional approaches. At the same time, the growing pressure of the I/O wall highlights the need for fundamental changes in interface concepts. This talk outlines how optical innovation across these layers contributes to shaping the next era of AI.
Edgar Auslander
Senior Director, Strategic Partnerships, Wearables, AR, AI, Meta
Edgar Auslander
Senior Director, Strategic Partnerships, Wearables, AR, AI, Meta
Bio:
Edgar Auslander has more 35 years of experience serving at company Boards, startups, a VC, and Fortune 100 companies. As Senior Director of Strategic Partnerships at Meta, he initiated and drove the partnership with EssilorLuxottica resulting in Ray-Ban Meta smart glasses. He is the Founding Managing Partner at Menlo Business Partners and was one of the founders of Texas Instruments' Wireless Business, bringing it from scratch to $5B/year. A former Faculty Member at Stanford University and the EDHEC Business School, he teaches Management of Change and Business Negotiation classes at UC Berkeley Extension. A Senior Member of IEEE, he is a Kauffman Fellow and holds an MBA from Columbia University, and an MEEng. from Cornell University.
Agnieszka Thonet
Senior Director of Technology, HP
Agnieszka Thonet
Senior Director of Technology, HP
Bio:
Agnieszka has over 23 years of digital transformation and product innovation experience. Recognized as a thought leader in emerging technologies and trends, she has a strong track record of managing and aligning global high performance multicultural teams to deliver strategic value.
Over the past 16 years she has held multiple technical and management roles across HP businesses. As Senior Engineering Director, she drove the delivery of full stack software on devices and to Enterprise customers. As Head of Innovation Partnerships, she gathered and led cross-industry, multidisciplinary research experts to create open collaboration models that unleashed impactful innovation. Her breadth of knowledge ranges from electronics and communication systems to digital manufacturing and complex cyber-physical architectures.
Fluent in four languages, she holds a MSc in Communication Systems Engineering from the University of the Basque Country in Spain.
Andrea Le Vot
Quantum Computing, Group Leader, Crédit Agricole
Thimothée Silvestre
Technology Foresight—Open Innovation Center, CEA
Thimothée Silvestre
Technology Foresight—Open Innovation Center, CEA
Bio:
After studying Biotechnology engineering, Timothée SILVESTRE worked as a biologist at the Swiss Institute of Experimental Cancer Research (ISREC) in Lausanne, and then as a research engineer at the Lyon Bioinformatics Pole (CNRS) after obtaining a degree in Computer Science. He worked on genetic sequence alignment algorithms as part of the European DataGrid computing project led by CERN. He earned an MBA from IAE Lyon3. After serving as an innovation expert in sustainable construction at ARIST (Burgundy Chamber of Commerce), he led the SPORALTEC cluster specializing in sports innovation. He joined CEA in 2015 as the head of the Ideas Laboratory, which he led for 4 years, and is currently focusing on technology monitoring and future-oriented missions at Y spot.
