Bio:

Mark Fuselier is senior vice president of Technology and Product Engineering al AMD. He is responsible for silicon and packaging technology development and new product introduction engineering. He played a central raie in the development and productization of computing solutions such as 2nm, multi-core CPU and GPU Soc integration, heterogenous APUs, 2.5D and 3D chip-packaging, and chiplet System in Package (SiP) integration. Fuselier holds a Master of Science degree in electrical engineering and Master of Business Administration from the University of Texas al Austin. He is a member of IEEE and the Electron Devices Society.

Abstract:

Fuselier will walk the audience through a systems-level cc-design approach that treats optics as a first-class element of advanced stacked and chipie! architectures (hybrid-bond 3D, 2.5D interposers, panel scaling). He will demonstrate the practical tradeoffs - thermal paths, power delivery (IVR), die-ta-die pitch and test strategies - and real examples of how tighter locality + optical offload reduces data-movement energy by orders of magnitude.