Bio:

Henri is part of ASML’s Customer Team EU/US technology organization, focusing on technology strategy and business development for mainstream TWINSCAN lithography systems. In this role, he partners with customers across Europe and the United States on future technology roadmaps, application challenges, and operational requirements, working with the broader ASML organization to translate customer needs into improvements in products and services.

Since 2019, Henri has led business development for ASML’s dry TWINSCAN systems, building on earlier contributions across different business line —including significant growth in the 200 mm TWINSCAN business.

Prior to ASML, Henri spent 18 years at Philips in the Netherlands and the United States, holding management roles in Research, Design & Engineering, and Sales. He joined ASML in 2006 and has worked on PAS5500 and TWINSCAN platforms.

Henri obtained an MSc in Physics (Drs.) from Utrecht Rijks University (the Netherlands).

Abstract:

The rapid growth of AI workloads is pushing data‑center energy consumption to its limits, accelerating the transition from electrical to optical interconnects. Silicon photonics, integrated lasers, and emerging microLED‑based communication architectures are key to sustaining bandwidth scaling while improving energy efficiency. As these technologies mature, lithography variability—rather than resolution—has become a dominant factor in optical loss, yield, and system‑level power efficiency. This keynote presents an optical-lithography‑centric view of optical interconnect scaling, framed by the ASML holistic triangle of scanner capability, process optimization, and design co‑optimization. Through concrete examples, the talk illustrates how resist selection and imaging conditions influence line‑edge roughness (LER) in critical photonic layers, and how LER directly impacts optical performance and energy efficiency. It further discusses practical methods to quantify LER and pattern variability using high‑throughput HMI metrology, enabling tighter process control. Finally, the use of curvilinear OPC is demonstrated as an effective design‑technology co‑optimization approach to mitigate LER‑induced variability without pushing resolution limits. Together, these examples highlight lithography as a system‑level enabler for energy‑efficient optical interconnects in AI data centers.