Speakers
Sébastien Dauvé
CEO, CEA-Leti
Sébastien Dauvé
CEO, CEA-Leti
Bio:
Sébastien Dauvé was named CEO of CEA-Leti effective on July 1, 2021, after more than twenty years of experience in microelectronics technologies and their applications, including clean mobility, medicine of the future, cybersecurity, and power electronics.
Sébastien Dauvé started his career at the French Armament Electronics Center, where he worked on developing synthetic-aperture radar. In 2003, he joined CEA-Leti as an industrial transfer manager and supervised several joint research laboratories, in particular with the multinational Michelin.
In 2007, Sébastien Dauvé became a laboratory manager, then head of an R&D department in the area of sensors applied to the Internet of things and electric mobility. During this time, he supported the dissemination of new technologies in industry, including the automotive industry (Renault), aeronautics, national defense (SAFRAN), and microchips with the industry leader Intel. He played an active role in the creation of start-ups in application fields ranging from health to infrastructure security, leading to dozens of new jobs. In 2016, he became Director of the CEA-Leti Systems Division.
From sensors to wireless communication, Sébastien Dauvé has played an active role in the digital transformation, focused on coupling energy frugality and performance. He has made cross-disciplinary approaches central to innovation by harnessing the expertise of talented teams with diverse backgrounds. Their goal is to provide technological tools for meeting the major societal challenges of the future.
Sébastien Dauvé is a graduate of the French Ecole Polytechnique and the National Higher French Institute of Aeronautics and Space (ISAE-SUPAERO).
Jean-René Lèquepeys
CTO, CEA-Leti
Jean-René Lèquepeys
CTO, CEA-Leti
Bio:
Jean-René Lèquepeys received an engineering degree in 1983 from CentraleSupélec, a top French graduate engineering school at Paris-Saclay University, France. He taught physics during 2 years in Ouarzazate, Morocco.
He joined CEA, a French Research and Technology Office focusing on applied research, in Paris Saclay in 1985. He first worked at the laboratory of the Central Security Office, on the evaluation of means of detection and intrusion. Two years later, he was promoted head of this laboratory.
In 1993, he moved to Grenoble, France, and joined the System Division of CEA-Leti. He worked on different projects in the field of image processing and telecommunication technologies. In particular, he was responsible for the "Telecom, Communicating Objects and Smart Card" programs from 1999 to 2004.
In 2005, he took the responsibility of the Circuits Design Division at CEA-Leti (200 people). He launched new research activities at CEA such as a new laboratory in Aix-en-Provence, France, on the development of secured chips. In 2000, Jean-René Lèquepeys received the prestigious award from the french Société de l'Electricité, de l'Electronique et des technologies de l'information et de la communication (SEE) "Grand Prix de l'électronique Général Ferrié" for his work in the telecommunications field (he holds 15 patents).
In 2010, he launched a new division at CEA focusing on Electronic Architectures, Integrated Circuit Design and Embedded Software. He established the structure on two sites (Paris and Grenoble) and led the division twice in his career.
He rapidly got involved in the creation of the Silicon Components Division at CEA-Leti, and took the lead of it in 2011 managing 350 people. Division encompasses micro and nanoelectronics (SOI, nanodots, quantum, memories, 3D technologies, substrates), Micro Systems (sensor, actuator, radiofrequency components) and Power Components. He established the French Nano2022 Program for research funding in microelectronics.
In 2019, he was appointed Chief Technology Officer of CEA-Leti, overseeing Science, relations with the European Commission, Industrial Partnership and Strategic Program Management in the scope of the institute (2,000 people, ~€350m budget). He took the responsibility of the Microelectronic Program at CEA level, spearheading technological and upstream research in the field of semiconductor technologies. For the past 2 years, he has been strongly involved in the CEA-Leti Next Gen FD-SOI project in the frame of France2030 and has played a key role in European chips Act pilot line promoting FD-SOI and Gate All Around technologies.
Having dedicated his career to applied research, he is regularly invited as a keynote speaker in international semiconductor conferences.
Jean-René is also Vice President of ACSIEL, a professional trade union gathering industrial companies in the French electronic value chain, member of the Board of EPOSS, the European Technology Platform on Smart Systems Integration, a member of the Board of AENEAS, the Association for Europoean NanoElectronics Activities, and an expert consultant for the European Commission and French Research Agency
Michael Tchagaspanian
EVP Strategic Partnerships, CEA-Leti
Michael Tchagaspanian
EVP Strategic Partnerships, CEA-Leti
Kaïs Mnif
Trixell, CEO
Kaïs Mnif
Trixell, CEO
Bio:
Kaïs Serves as CEO to Trixell, a joint venture between Thales, Siemens, and Philips specialized in X-ray flat panel detectors. He's also Head of the Radiology business at Thales.
Kaïs joined Thales in 2014 in Singapore as Business Development Director covering Asia. He then led the air traffic navigation aids Business of Thales, based in Milan.
Before joining Thales, he spent 18 years in the Automotive then the Railway industry where he held several management positions around the world.
Kais holds an engineering degree in automation and electronics from INSA Toulouse, a Master degree in enterprise administration from IAE Toulouse, and an MBA from INSEAD.
He's occasionally a guest lecturer in decision sciences, and multicultural leadership.
Abstract:
A bit like the concept of 'terroir' in wine making defines the unique combination of environmental factors and human practices in a specific location, industrial clusters are sometimes born from similar unique combinations.
Trixell was born from such favorable combinations of environmental factors : proximity with CEA and top universities, facilitated access to a large local talent pool, and a rich regional supply chain, to mention a few.
My presentation will quickly describe how about 30 years ago the flat panel detector was invented here, and why the next innovations in X-Ray imaging will continue to be invented here and what we're doing about it together with the CEA.
Hervé Bouaziz
President, Lynred
Hervé Bouaziz
President, Lynred
Bio:
Hervé Bouaziz was appointed executive President of LYNRED, a world leader in Infrared detectors, in December 2023. Prior to that he held various positions of responsibility within SAFRAN Group, as Director of Strategy and M&A within Safran Electronics and Defense, and as Director of Military Engines Programs within Safran Aircraft Engines. He also worked 20 years in Aerospace at DGA, the Defense Armament Procurement Agency of the French Ministry of Defense, on military aircraft Programs and as an Armament Attaché in Washington DC. Hervé is a graduate of Ecole Polytechnique, SupAéro, and the Industrial Colllege of the Armed Forces (USA). He also earned his wings as a military pilot in the Armée de l'Air et de l'Espace.
Abstract:
Infrared sensing and imaging is a fast expanding market due to its inherent unique characeritics
Trend is clearly toward high resolution, miniaturization, low power consumption and agile image correction with AI
Anticipation of high demand in mobility, industrial control, environment, Robotics, with applications involving the use of AI
Generalization of usage will draw a strong requirement for better competitivity, and high volume production capacity
LYNRED is gearing up to meet this challenge with its partners and its brand new CAMPUS manufacturing capability
Barbara De Salvo
Director of Research, META
Herman Boom
EVP Deep Business Line DUV, ASML
Thibault Basquin
Executive Board Co-Head, ARDIAN Buyout
Emmanuel De Gabory
General Manager Head of Research Lab, NEC
Erik Hadland
Director of Technology Policy, SIA
Hardware at the heart of AI
Pioneering precision sensing
Pierre-Damien Berger
MEMS Industrial Partnerships Manager, CEA-Leti
Pierre-Damien Berger
MEMS Industrial Partnerships Manager, CEA-Leti
Bio:
CEA-Leti is a leading MEMS R&D lab that supports the industry with the work of more than 150 people, making it the world’s largest MEMS R&D institute.
Pierre-Damien was previously the MinaSmart (European Digital Innovation Hub) director at Minalogic. He also worked as CPS European projects manager, Head of Smart Devices Program, Industrial Partnership Manager and VP Business Development & Communication at CEA-Leti.
With more than 25 years’ experience, 10 years in industry and 15 years in industry-geared R&D, his experience has allowed him to master the perfect balance between business and innovation: understand and listen to needs, identify and select innovative solutions, enhance functions that meet expectations, and finally, communicate to radiate.
Marc Sansa Perna
Project Manager, CEA-Leti
Marc Sansa Perna
Project Manager, CEA-Leti
Bio:
Marc Sansa obtained his Ph.D. degree in electronic engineering from the Universitat Autònoma de Barcelona, Barcelona, Spain, in 2013. He is an expert in microelectromechanical system (MEMS) sensors, RF MEMS and optomechanics, having co-authored over 50 publications and several patents. He is currently a project manager at the Sensors and Actuators Laboratory of CEA-Leti.
Abstract :
Electrical microsensors (MEMS) have been gaining maturity and performance during the last 40 years, and they are nowadays ubiquitous in our everyday life. Recently, the combination of MEMS and silicon photonics has given birth to optomechanical MEMS (optically transduced microsensors), enabling a jump in performance in terms of readout sensitivity and frequency of operation.
In this talk I will present the advantages of optomechanics for high-efficiency sensing, and how CEA-Leti’s developments have enabled novel applications in the fields of biosensing, environment/biological monitoring, high-speed AFM and clocks.
The FAMES Pilot Line
Dominique Noguet
FAMES Pilot Line Project Coordinator, CEA-Leti
Dominique Noguet
FAMES Pilot Line Project Coordinator, CEA-Leti
Bio:
Dominique Noguet holds an engineering degree of the National Institute of Applied Sciences (INSA) in electrical engineering in 1992, and a PhD from National Polytechnical Institute of Grenoble (INPG) in 1998. Then, he held several positions at CEA-Leti as a digital IC designer, lab manager and department manager. He led many projects at a national level and in several European frameworks (FP5, FP6, FP7). In January 2023, he was appointed project manager for the France 2030 flagship project NextGen. He is currently the coordinator of the FAMES Pilot Line and reports to CEA-Leti’s CEO. Dominique is a CEA senior expert and an IEEE Senior Member. He has authored or co-authored ~100 scientific papers (several best paper awards), several book chapters and 15 patents. He was a reviewer and a member of scientific committees of many conferences and a member of journal editorial boards. He was conference chair and TPC chair of several international conferences.
Abstract:
The goal of this presentation is to introduce the FAMES project and explain the technologies that have been developed. It will also explain how to use the FAMES pilot line, which can be accessed in various ways, including the open access mechanism. Finally, it will briefly introduce this first technical workshop and the future actions expected throughout the project.
Thierry Poiroux
Head of the Characterization, Design and Simulation Department, CEA-Leti
Thierry Poiroux
Head of the Characterization, Design and Simulation Department, CEA-Leti
Bio:
Thierry Poiroux received the M.S. degree in 1995 and the Ph.D. degree in 2000. He joined CEA–Leti as a Research Staff Member in 2000. Until 2002, he was involved in partially and fully depleted silicon-on-insulator (SOI) process integration and compact modeling. From 2002 to 2010, he worked on advanced device architectures and was in charge of multiple-gate device modeling, planar double gate process integration and fabrication of graphene-based transistors. In 2011 and 2012, he has been the Head of the Innovative Device Laboratory of CEA–Leti, dedicated to the development of advanced CMOS technologies. From 2012 to 2018, he developed the second version of the L–UTSOI compact model, selected by the Si2 Compact Model Coalition as a standard industrial model for fully-depleted SOI technologies. From 2018 to 2021, he was the head of the Simulation and Compact Model Laboratory of CEA–Leti, and since 2021, he is in charge of the Characterization, Design and Simulation Department. He has authored or coauthored five book chapters and about 190 papers and communications, and he is author or co-author of about 20 patents.
Abstract:
The presentation will review the physical specificities of FD-SOI transistors, highlighting analogies and differences with respect to bulk transistor behavior, and we will explain how to take advantage of this technology to design performant circuits.
Gabriel Pares
Project Manager, CEA-Leti
Gabriel Pares
Project Manager, CEA-Leti
Bio:
Gabriel Parès has an Engineer degree in “material science” from l’Institut National des Sciences Appliquées (INSA) de Lyon, France and a postgraduate degree in “semiconductor material sciences” from the University of Lyon.
He has been working for 32 years in semiconductors and MEMS industry in industrial and R&D fields, formerly for STMicroelectronics and MEMScap, then he joined CEA-leti in 2004.
He is currently project leader at CEA-Leti in the Laboratory of Memories and Computing in charge of the workpackage dedicated to embedded Non Volatile memories of the FAMES pilot line.
Abstract:
The presentation will address embedded Non-Volatile Memory (eNVM) devices integrated in the BEOL of advanced CMOS technologies starting from the 22nm and going towards the 10 and 7nm FD-SOI technology nodes. One of the goals of eNVM in the framework of FAMES is to open opportunities for disruptive IC architectures and designs using the most appropriate eNVM for the considered applications and use cases. OxRAM, FeRAM, BEOL FeFET and MRAM will be addressed in the presentation. Exploration of potential new applications will cover mainstream domains such as Artificial Inteligence and security for instance.
Claire Fenouillet-Beranger
Project Manager & FD-SOI process integration leader, CEA-Leti
Claire Fenouillet-Beranger
Project Manager & FD-SOI process integration leader, CEA-Leti
Bio:
Claire FENOUILLET-BERANGER (F) joined CEA-Leti, Grenoble, in 1998 where she carried out her PhD. work on the integration and characterization of SOI devices. From 2001 to 2013 she worked as a CEA-Leti assignee in advanced R&D STMicroelectronics center, Crolles, France on FD-SOI (Fully-depleted SOI) technology platform development and characterization. From 2013 to 2020 she worked as the project leader of the low temperature MOSFETs development for 3D sequential integration. From January 2020 to January 2022, she was the LETI SiC pilot line project manager in the frame of the joint development program between SOITEC & AMAT.
She is the author and co-author of more than 200 publications in major conferences and journals and of more than 40 patents. She was the co-recipient of the Grand Prix du Général Ferrié in 2012 for her
work on FD-SOI. She is in charge of CMOS patent portfolio. Since 2022, she is director of research, and CEA Fellow expert, and co-project manager of the FD-SOI next generation node integration at CEA-Leti.
Abstract:
The rising of emerging applications involving high energy efficiency, low power consumption and cost reduction requires the development of differentiating technologies. Fully-depleted Silicon on Insulator (FD-SOI) planar technology is an alternative to the FinFet in order to address a large range of applications thanks to its low process cost and complexity and its suitability to mixed-signal circuits. The advantages of the FD-SOI as compared to other planar technologies are the improvement of the electrostatic behavior thanks to the introduction of ultra-thin channel and Buried OXide layer (BOX), low parasitic capacitance, and low mismatch (low or no channel doping). However in order to fulfill the performance specifications of the 10nm down to the 7nm node, new technological boosters need to be developed.This presentation will deal with the specific electrical properties of FD-SOI devices (Thin silicon, thin BOX, back bias) and technological knobs for the 10-7nm nodes.
Somnath Pal
Scientist, Silicon Austria Labs
Somnath Pal
Scientist, Silicon Austria Labs
Bio:
I am Dr. Somnath Pal, a passionate researcher with a Ph.D. in Materials Science, specializing in engineering magnetic, high-κ dielectric, and multiferroic materials. My expertise lies in semiconductor device design, modeling, and microfabrication, with hands-on experience in thin film deposition techniques such as sputtering, e-beam evaporation, ALD, and PECVD. I have a strong background in photolithography, including e-beam lithography, and ICP/RIE etching processes. My skills extend to advanced microscopy techniques like SEM/EDS, FIB, AFM, and optical spectroscopy. I am well-versed in electrical characterization of fabricated devices, including IV, CV, and VNA measurements. Additionally, I have proficiency in simulation and statistical tools such as COMSOL, MATLAB, LabView, JMP, and Minitab. My research interests focus on RF MEMS development, particularly Piezo MEMS resonators, with the goal of advancing next-generation microsystems. Recently, I joined Silicon Austria Labs as a Scientist, contributing to the advancement of Magnetic Microsystems Technologies.
Abstract:
An RF circulator is a non-reciprocal, three-port passive device that enables directional signal flow between ports, ensuring isolation between transmit and receive paths. Traditional circulators depend on ferrite materials with external magnetic biasing, which limits integration and scalability. To address this, we focus on CMOS-compatible circulator designs utilizing barium hexaferrite (BaM) thin films for self-biasing, eliminating the need for bulky magnets. This talk presents the design, fabrication, and characterization of a self-biased RF circulator, emphasizing material selection, deposition techniques, and challenges in achieving uniform film quality and miniaturization. The characterization includes S-parameter analysis (S11, S21, S31) to assess insertion loss, isolation, and return loss.
We are fabricating and integrating these CMOS-compatible circulators for the FAMES pilot line, aiming to develop scalable, cost-effective, and high-performance RF circulators for next-generation wireless technologies.
Silicon photonics
Eléonore Hardy
Silicon Photonics Partnership Manager, CEA-Leti
Eléonore Hardy
Silicon Photonics Partnership Manager, CEA-Leti
Eleonore Hardy joined CEA-Leti in 2018 as a business developer in silicon photonics.She holds a Master's degree in Engineering and followed a MS in Management & Innovation. Eleonore has been working in the optics and photonics industry since 2005 and previously worked for Philips in the Netherlands and for Varioptic (a BU of Corning) in China.
During her career, Eleonore has been successful in creating long-term value in lasers in France, China and India for Quantel (Lumibird), and spectrometers in Europe and Asia for Resolution Spectra Systems. Eleonore is dedicated to developing new business opportunities in silicon photonics, especially in communications, sensing and high-performance computing.
Benoit Charbonnier
Research engineer, CEA-Leti
Benoit Charbonnier
Research engineer, CEA-Leti
Bio:
Benoit Charbonnier received his engineering degree in 1994 from Ecole Nationale Supérieure des Télécommunications de Paris and received his Ph.D. degree in 1997 on 40 Gbps soliton transmission from the same institution. In 1997, he joined Nortel Network in Harlow, UK, in the Advanced Communications group where he worked on 80 Gbps long haul transmission and then, in 2001, joined Marconi Communications to develop an Ultra-Long Haul 10 Gb/s based transmission products. In 2004, he joined Orange Labs as a research engineer, focusing on next generation optical access networks and particularly on digital signal processing applied to optical communications. In 2015, he moved to CEA-Leti, Grenoble, leading the photonics program within the French Institute of Technology Nanoelec, developing industrial partnerships to promote silicon photonics technologies. He is now in charge of neuromorphic photonics applications within the silicon photonics lab.
Abstract:
Computing with light is gathering interest recently with prospects of ultra high speed computations hence at very low power consumption per operation. Leti's Silicon Photonics Platform with integrated IIIV, Phase Change Materials and Barium Titanate is well suited to deliver high performance low power circuits for computing as well as inference.
The keys to sustainable ICs
Laurent Pain
Sustainable Electronics Program Director, CEA-Leti
Laurent Pain
Sustainable Electronics Program Director, CEA-Leti
Bio:
Laurent Pain is graduated from the Ecole Nationale Supérieure de Physique de Grenoble in 1992. He received his Ph D after his work on DUV resists study. He joined CEA-Leti in 1996 to work on infra-red technology, and then came back to STmicroelectronics in 1999 working on 193nm and e-beam lithography technologies.
From 2008 to 2014, Laurent Pain leaded the lithography laboratory of the silicon technology division of CEA-Leti. He was also managing in parallel the industrial consortium IMAGINE dedicated to the development of multibeam lithography with MAPPER lithography BV.
Since July 2014, within the CEA-Leti Silicon Technology Division, he is now in charge of the business and the partnerships developments of the Silicon Technologies Platform Division.
