Sebastien Ricavy (1977, Aug. 13) received the M.Sc. degree in electrical engineering and computer sciences fields in 2001 from Grenoble Alpes University, Grenoble, France.
He started his career focusing on design of standard cells and memories on SOI technologies (PD/FDSOI technologies) at SOISIC SA. From 2006 to 2018, he worked at ARM LTD where he was involved in SRAM, register files or VROM design activities as Senior Memory Technical Lead role or Memory Team Manager. Since 2019, he has been working as Memory Research Engineer at CEA, Grenoble, France. His research activities include various type of non-volatile technologies such as OxRAM, FeRAM or PCM designs.
Resistive RAM (RRAM) is a promising candidate to replace NOR eFlash in sub-40nm CMOS technologies. It offers low cost, high-speed and low-voltage embedded non-volatile memories compatible with CMOS back-end process. However, the stochasticity of RRAM programming limits the intrinsic performance of memory arrays without the use of advanced design assist techniques. The recent industrial adoption of RRAM in some major foundries has been done through a significant involvement of circuit design community to boost both the read-margin (RM) and endurance, while reducing the energy consumption.
In this talk, we will review different RRAM design assist techniques and we will demonstrate their impact on enhancing the intrinsic RRAM performance. Based on representative RRAM macro (130nm CMOS), statistic (176kb) and endurance (1M cycles) characterizations, we will show how pairing both process development and design solutions can push the intrinsic RRAM performance to the next level.