Bio:

Simon Moore is a Professor of Computer Engineering at University of Cambridge, Department of Computer Science and Technology (previously The Computer Laboratory) where he conducts research and teaching in the general area of computer architecture with particular interests in secure and rigorously-engineered processors and subsystems. Since 2010, he has led the microarchitecture work on CHERI for a number of ISAs including RISC-V. He is vice-chair of the CHERI special interest group at RISC-V International.