Bio:
Thierry Poiroux received the M.S. degree in 1995 and the Ph.D. degree in 2000. He joined CEA–Leti as a Research Staff Member in 2000. Until 2002, he was involved in partially and fully depleted silicon-on-insulator (SOI) process integration and compact modeling. From 2002 to 2010, he worked on advanced device architectures and was in charge of multiple-gate device modeling, planar double gate process integration and fabrication of graphene-based transistors. In 2011 and 2012, he has been the Head of the Innovative Device Laboratory of CEA–Leti, dedicated to the development of advanced CMOS technologies. From 2012 to 2018, he developed the second version of the L–UTSOI compact model, selected by the Si2 Compact Model Coalition as a standard industrial model for fully-depleted SOI technologies. From 2018 to 2021, he was the head of the Simulation and Compact Model Laboratory of CEA–Leti, and since 2021, he is in charge of the Characterization, Design and Simulation Department. He has authored or coauthored five book chapters and about 190 papers and communications, and he is author or co-author of about 20 patents.