Bio :

Philippe Garnier is an R&D senior Expert for Materials and Surface Preparation in semiconductors manufacturing at STMicroelectronics, Crolles, France. He earns his MS in Chemistry in 1999 from ENSIACET, Toulouse, France. He has been working within severall Alliances: first for Philips Semiconductors in 2001 within the Crolles2 Alliances, then for STMicroelectronics within the IBM Alliance in East Fishkill, NY, USA. With 25 years' experience in the wet area, he has demonstrated strong skills in the development of first wet single wafer tools, gate oxide patterning. He has supervised 7 PhD studies on various topics (wetting, acoustics, wet chemistries' infiltration through polymeric films, particles removal ...) and published more than 60 papers in international conferences.