Bio:

Michael studied electrical engineering at the Technical University of Stuttgart.
In 1998, he joined Bosch in Stuttgart as hardware development engineer for Engine Control Units. 2001, he joined ETAS GmbH in Stuttgart as a Product Manager for Rapid Prototyping system. He left ETAS 2011, when he was Director for Product Management and Development and responsible for all ETAS HW. After ETAS Michael became Vice President at BOSCH and was the Head of Center of Competence for Vehicle Electrics and Electronics Architecture. In this role he was responsible for future E/E-Architecture’s development incl. responsibility for recognizing and assigning new technologies. In 2015 he moved to BOSCH Japan and was the Head of Customer Engineering responsible for Asian Pacific Engine Control Units & SW Service Business. In 2019 he came back to Germany and became Head of HW Development for Powertrain Control Systems BOSCH. In 2020 he was founding member of the new BOSCH Division XC (Cross-Domain Computing Solutions) and had the role as the head of Product Group responsible for Base-SW and Middleware incl. OS Product & Services. Since 07/2022 he joined BOSCH Tier2 as a SCP responsible for Chiplet.

Abstract:

The CHASSIS initiative marks a transformative step in automotive compute platform design for Software-Defined Vehicles (SDVs). By leveraging chiplet-based architectures, CHASSIS addresses the inherent limitations of traditional monolithic System-on-Chips (SoCs), introducing a modular and scalable approach to semiconductor design. This paradigm shift enables tailored, high-performance computing solutions that accelerate the transition to software-defined mobility and foster competitive innovation across the automotive industry.
Our vision extends beyond technical advancement: CHASSIS aims to restore European technological sovereignty in automotive semiconductor innovation through the creation of a multi-vendor chiplet ecosystem. This ecosystem ensures architectural flexibility, automotive-grade reliability, and freedom from proprietary constraints, paving the way for open, future-proof compute platforms.
By delivering scalable architectures that meet diverse performance requirements,