Bio:

Masanori Tsukamoto received the B.S. and M.S. degrees in electric engineering from Chiba University, Chiba, Japan, in 1988 and 1990, respectively. Since 1990, he has been with the semiconductor business group, Sony Corporation, Atsugi, Japan, where he has been working on the technology development and manufacturing operation of 250-, 180-, 90-, 45- and 22nm-node SRAMs and CMOS LSIs. He is currently a Senior Manager in the memory technology department, Sony Semiconductor Solutions Corp. and engaged in the development of the emerging memory device.

Abstract :

For the edge AI applications, emerging memories such as RRAM, MRAM are potential candidates to address these concerns. However, these memories require high write energy consumption due to a current driven switching. Recently, a hafnium oxide based ferroelectric technologies have been strongly focused. We experimentally demonstrate 1T1C FeRAM memory array for the first time.
Deep neural network (DNN) inference for edge AI requires low power operation. We demonstrated it by implementing massively parallel matrix-vector multiplications (MVM) in the analog domain on highly resistive memory array. We propose a 1T1R compute cell (1T1R-cell) using FeFET and tunneling junction of MΩ resistor (MOR) for analog in-memory computing (AiMC).