Bio :

Jean Charbonnier, is graduated from National School of Physics of Grenoble in 2001 and obtained his Phd degree in crystallography from University Joseph Fourier of Grenoble in 2006. He joined the 3D wafer level packaging group of CEA-Leti in 2008. He has been working for more than 15 years in Through silicon vias, 3D interconnections and silicon interposers technology. His research interests include High Performance computing, Silicon Photonics Interposer as well as cryo-packaging for Quantum architecture applications. He is currently in charge of coordinating the High Density 3D Integration group within the 3D Integration Technologies Laboratory of CEA-Leti.

Abstract :

Due to the increasing costs of advanced nodes and the difficulties of shrinking analog and circuit input-output signals (IOs), alternatives to single die architectures are becoming mainstream. Scalable modular architectures and function partitioning paves the way for new system approaches using 3D technologies. 3D interconnects offers a breakthrough in terms of density, bandwidth, and limit overall power consumption. CEA-Leti’s advanced heterogeneous packaging research leverages expertise in 3D integration by means of Through Silicon Via (TSV) and Hybrid Bonding (HB) technologies developments since more than 15 years. This presentation will exposed the synergy of these key enablers through two meaningful examples for edge IA sensors and HPC applications.