Bio :

Dale is currently the Chief Strategist for IBM Research Chiplet and Advanced Packaging Group based in Albany, New York. Prior to his current role, Dale was Senior Manager and Senior Technical Staff Member at IBM Research with responsibility for developing and leading IBM’s Heterogeneous Integration Research Program and principal investigator in the IBM AI Hardware Research Center. Over his 30 + year career at IBM, Dale has held various technical, managerial, and business development positions in both advanced packaging and CMOS logic R&D. Dale received his PhD in Chemical Engineering from Virginia Tech with a focus on polymeric materials. Dale has co authored numerous research papers and holds multiple patents in the field of microelectronics.

Abstract :

High performance computing (HPC) and AI applications are driving capacity and complexity of computational workloads at an ever increasing rate. In order to sustain these trends and improve energy efficiency, new hardware technologies and architectures are required. Silicon scaling and design innovations will not be sufficient to meet this challenge. Innovations in advanced packaging, heterogeneous integration, and chiplet architectures hold great promise to deliver system level performance improvements for these critical workloads and provide energy efficiency improvements for the next decade and beyond. In particular, the ability to package multiple silicon chips with a variety of computational functions and technologies in a small form factor will be critical. Furthermore, these technologies must also deliver significant gains in chip to chip communication bandwidth and latency to realize the system level improvements required to sustain these trends and meet the needs of future applications. This talk will discuss trends in workload requirements for HPC / AI and how innovations in packaging and heterogenous integration can enable new hardware architectures to meet the needs of the future.