Bio:

Claire Fenouillet-Béranger joined CEA-Leti, Grenoble, in 1998 where she carried out her PhD. work on the integration and characterization of SOI devices. From 2001 to 2013 she worked as a CEA-Leti assignee in advanced R&D STMicroelectronics center, Crolles, France on FD-SOI (Fully-depleted SOI) technology platform development and characterization. From 2013 to 2020 she worked as the project leader of the low temperature MOSFETs development for 3D sequential integration. From January 2020 to January 2022, she was the LETI SiC pilot line project manager in the frame of the joint development program between SOITEC & AMAT. She is the author and co-author of more than 200 publications in major conferences and journals and of more than 40 patents. She was the co-recipient of the Grand Prix du Général Ferrié in 2012 for her work on FD-SOI. She is in charge of CMOS patent portfolio. Since 2022, she is director of research, and CEA Fellow expert, and co-project manager of the FD-SOI next generation node integration at CEA-Leti.

Abstract:

In the context of 10 nm FD-SOI technology development, new architectural and process building blocks must be implemented to meet the targeted device performance specifications. Strain engineering remains one of the primary performance boosters. Strain can be introduced either at the wafer level or at the device level. Additional process modules are required to further reduce access resistance and enhance overall device performance. In particular, the integration of in-situ doped, faceted raised source and drain regions is critical. Achieving the aggressive contacted poly pitch (CPP) target of 68 nm necessitates the implementation of advanced patterning techniques, specifically Self-Aligned Double Patterning (SADP), to meet density scaling requirements. In this presentation, we’ll dive into each of these levers and explore how they can push FD-SOI to the next level.