The FAMES Pilot Line
Empowering the next generation of European chips
The FAMES Pilot Line provides chipmakers, startups, fabless companies and academics with a pathway to high-performance, low-power chips. Learn how you can explore advanced FD-SOI 10 nm and 7 nm process technologies, embedded non-volatile memories, 3D integration, RF components, and power management integrated circuit solutions.
Welcome Coffee, Exhibition & Networking
09:30 a.m. - 11:30 a.m. | Morning Session
Co-chairs
Dominique Noguet
FAMES Pilot Line Project Coordinator, CEA-Leti
Susana Bonnetier
FAMES Pilot Line Open Access Chairperson, CEA-Leti
Laurent Fesquet
Deputy Director of the TIMA Laboratory, Grenoble INP
Dominique Noguet
FAMES Pilot Line Project Coordinator, CEA-Leti
Fames Pilot Line opportunities for advanced chip design ...more info
Thierry Poiroux
Head of the Characterization, Design and Simulation Department, CEA-Leti
Taking advantage of FD-SOI transistor specificities ...more info
Claire Fenouillet-Beranger
Project Manager, CEA-Leti
UTBB FD-SOI and key enablers for next generation node : a strategic EU-made technology ...more info
Gabriel Pares
Project Manager, CEA-Leti
Non volatile memories for Embedded solutions on 22 nm FD-SOI node and beyond, technologies and applicative circuits development ...more info
Get some Fresh Ideas: 180 secs Pitch by a talented young scientist
Panel session : Fames Pilot Line Open Access opportunities
The purpose of this roundtable discussion is to provide a forum for the exploration of the concept of Open Access within the context of the FAMES pilot, with a particular emphasis on the various access mechanisms available. A significant portion of the discussion will be dedicated to the 2025 Open Access offer, with a focus on its implications and the potential implications for stakeholders.
Susana Bonnetier, CEA Leti; Laurent Fesquet, Grenoble INP; Dr. Sambuddha Khan, Tyndall; (from left to right)
Lunch, Exhibition & Networking
- Latest Demos: Discover more than 50 live demos and network with potential partners.
- Startups Corner: Don’t miss out on the startup corner to learn about the latest tech offers.
- Business Meetings: Book meetings with experts to discuss your innovation project.
02:30 p.m. - 05:30 p.m. | Afternoon Session
Cian O'Mathuna
Director Integrated Power and Energy Systems, Tyndall National Institute
Micro-inductors on silicon for integrated dc-dc converters ... more info
Cédric Rolin
Program Manager, IMEC
E-score for reducing the environmental footprint of IC chip manufacturing ... more info
Get some Fresh Ideas: 180 secs Pitch by a talented young scientist
Panel session : FAMES Academy Essential skills for designing in FD-SOI
FAMES includes a dedicated training work package to train engineers and technicians with the skills to leverage FD-SOI technology and design circuits using advanced setups. The FAMES pilot line aims at developing new technological nodes, such as 10 nm and beyond, enabling European companies to create innovative IPs for cutting-edge applications. However, the success of the project hinges on having skilled professionals. Therefore, it is imperative for European company employees and talented microelectronics graduates to acquire specialized knowledge and expertise in FD-SOI technology design and characterization.
Laurent Fesquet, Grenoble INP; Cian O'Mathuna, Tyndall; (from left to right)
Coffee Break, Exhibition & Networking
Bonus: Attendees will receive the conference proceedings after the event
The FAMES Pilot Line of the Chips JU (2023-2028) is funded by Horizon Europe under GA 101132237, Digital Europe under GA 101182297, Partners’ National Public Authorities and the ANR NextGen project ANR-22-NEXTG-001 of the France 2030 initiative
